NCV7754DPR2G Datasheet NCV7754DPR2G | P19-P21

NCV7754

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TER Information Retrieval

TER information retrieval is as simple as bringing CSB high−to−low. No clock signals are required.

B9B10B11B12B13B14

B15

CSB

SCLK

MSB

B15

B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1

LSB

B1B2B3B4B5B6

TER

Figure 27. Serial Peripheral Interface

The timing diagram highlighted in Figure 27 shows the SPI interface communication.

Note:

1. The MSB (most significant bit) is the first transmitted bit.

2. Data is sampled from SI on the falling edge of SCLK

3. Data is shifted out from SO on the rising edge of SCLK

4. SCLK should be in a low state when CSB makes a transition.

Frame Detection

Input word integrity (SI) is evaluated by the use of a frame consistency check. The word frame length is compared to an

n * 8 bit (where n is an integer) acceptable word length (16−bit minimum) before the data is latched into the input register. This

guarantees the proper word length has been imported and allows for daisy chain operation applications with 8−bit SPI devices.

The frame length detector is enabled with the CSB falling edge and the SCLK rising edge.

Reference the valid SPI frame shown below. (Figure 27)

CSB

SCLK

B7 B6 B5 B4 B3 B2 B1 B0

Frame detection starts

after the CSB falling edge

and the SCLK rising edge.

Internal Counter 9 10

11 12 13 14 15 16

Frame detection mode ends with

CSB rising edge.

Valid 16 bits shown

345678

B15 B14 B13 B12 B11 B10 B9 B8

Figure 28. Frame Detection

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DAISY CHAIN SETUP

Serial Connection

Daisy chain setups are possible with the NCV7754. The serial setup shown in Figure 29 highlights the NCV7754 along with

any 16 bit device using a similar SPI protocol. Particular attention should be focused on the fact that the first 16 bits which are

clocked out of the SO pin when the CSB pin transitions from a high to a low will be the Diagnostic Output Data from the Fault

Output Register. These are the bits representing the status of the IC. Additional programming bits should be clocked in which

follow the Diagnostic Output bits. The timing diagram shows a typical transfer of data from the microprocessor to the SPI

connected IC’s.

IC4

NCV7754

CSB SCLK

IC3

CSB SCLK

IC2

CSB SCLK

using 16 Bit

SPI

protocol

CSB SCLK

microprocessor

IC1

using 16 Bit

SPI

protocol

using 16 Bit

SPI

protocol

Figure 29. Serial Daisy Chain

{

CSB

SCLK

CMD 2nd CMD 3rd CMD 4th CMD

Figure 30. Serial Daisy Chain Timing Diagram

Table 2. SERIAL DAISY CHAIN DATA PATTERN

CLK = 16 bits CLK = 32 bits CLK = 48 bits CLK = 64 bits

IC4 1st CMD 2nd CMD 3rd CMD 4th CMD

IC3 IC4 DIAG 1st CMD 2nd CMD 3rd CMD

IC2 IC3 DIAG IC4 DIAG 1st CMD 2nd CMD

IC1 IC2 DIAG IC3 DIAG IC4 DIAG 1st CMD

micro IC1 DIAG IC2 DIAG IC3 DIAG IC4 DIAG

Table 2 refers to the transition of data over time of the Serial Daisy Chain setup of Figure 29 as word bits are shifted through

the system. 64 bits are needed for complete transport of data in the example system. Each column of the table displays the status

after transmittal of each word (in 16 bit increments) and the location of each word packet along the way.

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8−bit Devices

The NCV7754 is also compatible with 8 bit devices due to the features of the frame detection circuitry. The internal bit

counter of the NCV7754 starts counting clock pulses when CSB goes low. The 1st valid word consists of 16 bits and each

subsequent word must be comprised of just 8−bits (reference the Frame Detection Section).

IC2

NCV7754

CSB SCLK

IC1

CSB SCLK

microprocessor

Any IC

using 8 Bit

SPI

protocol

The NCV7754

is also

compatible with

8−bit devices

Compatibility

Note the SCLK timing requirements of the NCV7754.

Data is sampled from SI on the falling edge of SCLK.

Data is shifted out of SO on the rising edge of SCLK.

Devices with similar characteristics are required for

operation in a daisy chain setup.

Figure 31. Serial Daisy Chain with 8−bit Devices

Parallel Connection

A more efficient way (time focused) to control multiple SPI compatible devices is to connect them in a parallel fashion and

allow each device to be controlled in a multiplex mode. Figure 32 shows a typical connection between the microprocessor or

microcontroller and multiple SPI compatible devices. In a serial daisy chain configuration, the programming information for

the last device in the serial string must first pass through all the previous devices. The parallel control setup eliminates that

requirement, but at the cost of additional control pins from the microprocessor for each individual CSB (chip select bar) pin

for each controllable device. Serial data is only recognized by the device that is activated through its respective CSB pin.

Figure 33 shows the waveforms for typical operation when addressing IC1.

CSB3

SCLK

CSB2

CSB1

NCV7754

CSB

SCLK

microprocessor

OUT1

OUT2

OUT3

NCV7754

CSB

SCLK

OUT1

OUT2

OUT3

NCV7754

CSB

SCLK

OUT1

OUT2

OUT3

CSB

chip1

CSB

chip2

CSB

chip3

SCLK

IC1

IC2

IC3

Figure 32. Parallel Connection Figure 33. Parallel Connection Timing Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

NCV7754DPR2G

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Gate Drivers OCTAL LOW SIDE RELAY DRIVER

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