NCV7754DPR2G Datasheet NCV7754DPR2G | P22-P24

NCV7754

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Stepper Motor Operation

The NCV7754 device is capable of driving stepper motors. Each stepper motor requires 4 low−side drive outputs.

Consequently, each NCV7754 device is capable of driving two stepper motors. Figure 34 below illustrates a Unipolar stepper

motor setup. For proper operation, the code listed in Table 3 should be used (and repeated) for one way operation (clockwise).

For reverse direction, simply reverse the code and repeat (counterclockwise). Outputs 1−4 are utilized for one stepper usage.

For a 2

stepper motor, repeat the code used for outputs 1−4 to outputs 5−8. During operation waveforms similar to Figure 35

can be expected on the OUTx pins.

Figure 34. Stepper Motor Operation Setup

OUT4OUT3OUT2OUT1

NCV7754

STEPPER

MOTOR

Figure 35. Typical Stepper Motor Waveform (OUTx)

(Unipolar Portescap 35L048L32U)

BAT

= 12 V

Table 3. NCV7754 STEPPER MOTOR CODE

OUT 4 OUT 3 OUT 2 OUT 1

OFF ON OFF ON

ON OFF OFF ON

ON OFF ON OFF

OFF ON ON OFF

{Repeat}

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Input Register(via SPI)

Output On / Off Control

Output Register(via SO)

Open Load / (Over Load or

Over temperature)

Fault Output Register

SPI

CSB

SCLK

00=Stand−by Mode

01=Input Mode

10=ON Mode

11=OFF Mode

Transmission Error Bit – Only valid from CSB going low to

SCLK going high.

Command

Figure 36. SPI Register Overview

Figure 36 displays the functions controlled and reported via the SPI port.

The input register controls the input source (parallel or SPI) and the SPI input data.

The output register transmits the output fault bits and the frame detection integrity.

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SI SPI Input Data (16-bit serial structure of input word)

The 16−bit data received (SI) is decoded into instructions for each channel per the table below.

After a power−on reset, all register bits are set to a 1.

Table 4. SPI INPUT DATA

Channel 8 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1

MSB LSB

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

INPUT DATA REGISTER

Field

Bits Description

channel x

(x = 1−8)

15, 14

13, 12

11, 10

9, 8

7, 6

5, 4

3, 2

1, 0

Command

Channel Stand−by Mode

Fast channel turn off

Corresponding Channel Fault Register reset

Diagnostic Current Disabled

Input Mode

Channel Input directed to INx.

(reference PWM operation section).

Diagnostic Current Enabled in OFF State.

ON Mode

Channel turned on.

Diagnostic Current Disabled

OFF Mode

Channel turned off.

Diagnostic Current Enabled (Disabled after POR)*

*For proper LED load operation.

SO (fault diagnostic retrieval)

Output fault diagnostics from the output fault diagnostic register are shifted out on any 16 bit word clocked into Serial Input

(SI).

Output fault diagnostics and frame detection errors are available through the serial output (SO).

Table 5. SPI OUTPUT DATA

TER OL8 D8 OL7 D7 OL6 D6 OL5 D5 OL4 D4 OL3 D3 OL2 D2 OL1 D1

FAULT DIAGNOSTIC REGISTER

Field

Bits Description

TER CSB high−to−low

prior to 1st

SCLK low−to−high

Transmission Error.

0 Successful transmission in previous communication.

1 Frame detection error in previous transmission

or exiting Limp Home Mode, exiting UVLO Mode, or exiting Low Iq mode to Global Off Mode

Oln

(n = 1 − 8)

1, 3, 5,

7, 9, 11,

13, 15

Open Load

0 Normal Operation

1 Fault detected

(n = 1 − 8)

0, 2, 4,

6, 8, 10,

12, 14

Over Load or Over Temperature

0 Normal Operation

1 Fault detected

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

NCV7754DPR2G

Mfr. #:

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Manufacturer:

ON Semiconductor

Description:

Gate Drivers OCTAL LOW SIDE RELAY DRIVER

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