MOTOROLA
MPC823 Mobile Computing Microprocessor
9
Twelve serial DMA channels support the SCCs, SMCs, USB channel, SPI, and I
2
C controllers. The
independent DMAs give you two channels for general-purpose DMA usage. They offer high-speed
transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic.
The RISC microcontroller is the only block that can access the IDMA registers directly. The CPU
can only access them indirectly via a buffer descriptor.
System Interface Unit
The system interface unit supports traditional 68K big-endian memory systems, traditional x86
little-endian memory systems, and PowerPC little-endian memory systems. It also provides power
management functions, reset control, a PowerPC decrementer, timebase, and real-time clock.
Although the PowerPC core is a 32-bit device internally, it can be configured to operate with an 8-,
16-, or 32-bit data bus. Regardless of the system bus size, dynamic bus sizing is supported, which
allows 8-, 16-, and 32-bit peripherals and memory to coexist on a 32-bit system bus.
The memory controller supports as many as eight memory banks with glueless interfaces to
DRAM, SRAM, EPROM, Flash EPROM, SDRAM, EDO and other peripherals with two-clock
initial access to external SRAM and bursting support. It provides variable block sizes between 32K
and 256M. The memory controller has 0 to 20 wait states for each bank of memory and can use
address-type matching to qualify each memory bank access. It provides four byte-enable signals
for varying width devices, one output-enable signal, and one boot chip-select that is available at
reset.
The DRAM interface supports 8-, 16-, and 32-bit ports and uses a programmable state machine to
support almost any memory interface. Memory banks can be defined in depths of 256K, 512K, 1M,
2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In addition, the memory depth can be defined
as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit memory. The DRAM controller
supports page mode access for successive transfers within bursts. The MPC823 supports a glueless
interface to one bank of DRAM, while external buffers are required for additional memory banks.
The refresh unit provides CAS
before RAS, a programmable refresh timer, refresh active during
external reset, disable refresh modes, and stacking for a maximum of seven refresh cycles.
Video/LCD Controller
The MPC823 has a dual-purpose video/LCD controller that shares common dual-port memory.
However, only one of the controllers can be run at a time.
The video controller can be used to drive a digital NTSC/PAL encoder or a wide variety of digital
LCD panels. The frame buffer is stored in system memory in the form of an orthogonal matrix—
rows and columns. The 24-bit color data is organized as pixel components whether it is sequential
RGB or YC
r
C
b
. The video controller uses a dedicated DMA channel to read the display data from
the frame buffer and drive it to the video interface. It also generates the required timing signals,
such as horizontal sync, vertical sync, field, and blanking.
The LCD controller provides extremely versatile LCD support for 8-bit color, monochrome or
4/16-level grayscale, color TFT (12 bits, 4x3 RGB), and passive color (xSTN) 4/8 bit data. The
controller supports 4- or 8-bit single-scan, 2+2 bit dual-scan, or 4+4 bit dual-scan. It is
programmable for frame rate, number of pixels per line, and number of lines per frame. The panel
voltage is programmable through the duty cycle for contrast adjustments implemented in the
communication processor RISC timer PWM mode. Display data is stored in memory space and is
transferred into the controller using the DMA channel.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
