6
FN9257.2
March 7, 2008
LX (Pin 7/8)
This pin connects to the source of the top-side MOSFET and
the drain of the bottom-side MOSFET. This pin represents
the return path for the top-side gate driver. During normal
switching, this pin is used for top-side current sensing.
TGATE (Pin 8/9)
Connect TGATE to the top-side MOSFET gate. This pin
provides the gate drive for the top-side MOSFET.
BOOT (Pin 9/10)
This pin provides bias to the top-side MOSFET driver. A
bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND (Pin 10/11)
This is the power ground connection. Tie the bottom-side
MOSFET source and board ground to this pin.
BGATE (Pin 11/12)
Connect BGATE to the bottom-side MOSFET gate. This pin
provides the gate drive for the bottom-side MOSFET.
PVCC (Pin 12/13)
Provide an 8V to 14V bias supply for the bottom-side gate
drive to this pin. This pin should be bypassed with a
capacitor to PGND.
VCC (Pin 13/14)
Provide an 8V to 14V bias supply for the chip to this pin. The
pin should be bypassed with a capacitor to GND.
FSET (Pin 14/1)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
FSET
) from this pin to GND, the
switching frequency is set from between 200kHz and
1.5MHz according to Equation 1:
Alternately ISL8104’s switching frequency can be lowered
from 200kHz to 50kHz by connecting the FSET pin with a
resistor to VCC according Equation 2:
TSOC (Pin 15/2)
The current limit is programmed by connecting this pin with a
resistor and capacitor to the drain of the top-side MOSEFT.
A 200µA current source develops a voltage across the
resistor which is then compared with the voltage developed
across the top-side MOSFET. A blanking period of 120ns is
provided for noise immunity.
SSDONE (QFN ONLY Pin 16)
Provides an open drain signal at the end of soft-start.
Functional Description
Initialization
The ISL8104 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the bias voltage at the VCC pin and the driver input on the
PVCC pin. When the voltages at VCC and PVCC exceed
their rising POR thresholds, a 30µA current source driving
the SS pin is enabled. Upon the SS pin exceeding 1V, the
ISL8104 begins ramping the non-inverting input of the error
amplifier from GND to the System Reference. During
initialization the MOSFET drivers pull TGATE to LX and
BGATE to PGND.
Soft-Start
During soft-start, an internal 30µA current source charges the
external capacitor (C
SS
) on the SS pin up to ~4V. If the
ISL8104 is utilizing the internal reference, then as the SS pin’s
voltage ramps from 1V to 3V, the soft-start function scales the
R
FSET
kΩ[]
6500
F
s
kHz[]200 kHz[]–
-------------------------------------------------------
1.3–
⎝⎠
⎛⎞
kΩ≈
(R
FSET
to GND)
(EQ. 1)
R
FSET
kΩ[]
55000
200 kHz[]F
s
kHz[]–
-------------------------------------------------------
70+
⎝⎠
⎛⎞
kΩ≈
(R
FSET
to VCC)
(EQ. 2)
FIGURE 1. R
FSET
RESISTANCE vs FREQUENCY
10k 100k 1M
SWITCHING FREQUENCY (Hz)
RESISTANCE (kΩ)
10
100
1000
R
FSET
PULLUP
TO VCC
R
FSET
PULL-DOWN
TO GND
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
80
70
60
50
40
30
20
10
0
I
PVCC+VCC
(mA)
SWITCHING FREQUENCY (Hz)
C
GATE
= 1000pF
C
GATE
= 3300pF
C
GATE
= 10pF
ISL8104
