7
FN9257.2
March 7, 2008
reference input (positive terminal of error amp) from GND to
VREF (0.597V nominal). If the ISL8104 is utilizing an
externally supplied reference, when the voltage on the SS pin
reaches 1V, the internal reference input (into the error amp)
ramps from GND to the externally supplied reference at the
same rate as the voltage on the SS pin. Figure 3 shows a
typical soft-start interval. The rise time of the output voltage is,
therefore, dependent upon the value of the soft-start
capacitor, C
SS
. If the internal reference is used, then the
soft-start capacitance value can be calculated through
Equation 3:
If an external reference is used then the soft-start
capacitance can be calculated through Equation 4:
Prebiased Load Start-up
Drivers are held in tri-state (TGATE pulled to LX, BGATE
pulled to PGND) at the beginning of a soft-start cycle until
two PWM pulses are detected. The bottom-side MOSFET is
turned on first to provide for charging of the bootstrap
capacitor. This method of driver activation provides support
for start-up into prebiased loads by not activating the drivers
until the control loop has entered its linear region, thereby
substantially reducing output transients that would otherwise
occur had the drivers been activated at the beginning of the
soft-start cycle.
SSDONE
Soft-start done is only available in the 16 Ld QFN packaging
option of the ISL8104. When the soft-start pin reaches 4V, an
open drain signal is provided to support sequencing
requirements. SSDONE is deasserted by disabling of the part,
including pulling SS low, and by POR and OCP events.
Oscillator
The oscillator is a triangular waveform, providing for leading
and falling edge modulation. The peak-to-peak of the ramp
amplitude is set at 1.9V and varies as a function of frequency.
At 50kHz the peak to peak amplitude is approximately 1.8V
while at 1.5MHz it is approximately 2.2V. In the event the
regulator operates at 100% duty cycle for 64 clock cycles an
automatic boot cap refresh circuit will activate turning on
BGATE for approximately 1/2 of a clock cycle.
Overcurrent Protection
The OCP function is enabled with the drivers at start-up.
OCP is implemented via a resistor (R
TSOC
) and a capacitor
(C
TSOC
) connecting the TSOC pin and the drain of the
top-side MOSEFT. An internal 200
mA current source
develops a voltage across R
TSOC
, which is then compared
with the voltage developed across the top-side MOSFET at
turn on as measured at the LX pin. When the voltage drop
across the MOSFET exceeds the voltage drop across the
resistor, a sourcing OCP event occurs. C
TSOC
is placed in
parallel with R
TSOC
to smooth the voltage across R
TSOC
in
the presence of switching noise on the input bus.
A 120ns blanking period is used to reduce the current
sampling error due to leading-edge switching noise. An
additional simultaneous 120ns low pass filter is used to
further reduce measurement error due to noise.
OCP faults cause the regulator to disable (top- and
bottom-side drives disabled, SSDONE pulled low, soft-start
capacitor discharged) itself for a fixed period of time, after
which a normal soft-start sequence is initiated. If the voltage
on the SS pin is already at 4V and an OCP is detected, a
30μA current sink is immediately applied to the SS pin. If an
OCP is detected during soft-start, the 30µA current sink will
not be applied until the voltage on the SS pin has reached 4V.
This current sink discharges the C
SS
capacitor in a linear
fashion. Once the voltage on the SS pin has reached
approximately 0V, the normal soft-start sequence is initiated. If
the fault is still present on the subsequent restart, the ISL8104
C
SS
30μAt
SS
⋅
2V
----------------------------
=
(EQ. 3)
C
SS
30μAt
SS
⋅
V
REFEXT
----------------------------
=
(EQ. 4)
FIGURE 3. TYPICAL SOFT-START INTERVAL
V
EN
V
OUT
V
SS
t
SS
FIGURE 4. TYPICAL OVERCURRENT PROTECTION
V
SSDONE
V
SS
I
LOAD
t
HICCUP
I
OCP
ISL8104
