EL4581CSZ-T7 Datasheet EL4581CSZ, EL4581CSZ-T13, EL4581CSZ-T7 | P7-P9

FN7172.2

November 12, 2010

Description of Operation

A simplified block diagram is shown in Figure 13. The

following description is intended to provide the user with

sufficient information to be able to understand the effects

that the external components and signal conditions have on

the outputs of the integrated circuit.

The video signal is AC coupled to pin 2 via the capacitor C

nominally 0.1µF. The clamp circuit A1 will prevent the input

signal on pin 2 going any more negative than 1.5V, the value

of reference voltage V

. Thus the sync tip, the most

negative part of the video waveform, will be clamped at 1.5V.

The current source I

, nominally 10µA, charges the coupling

capacitor during the remaining portion of the H line,

approximately 58µs for a 15.75kHz timebase. From I•t = C•V,

the video time-constant can be calculated. It is important to

note that the charge taken from the capacitor during video

must be replaced during the sync tip time, which is much

shorter, (ratio of x12.5). The corresponding current to restore

the charge during sync will therefore be an order of

magnitude higher, and any resistance in series with C

will

cause sync tip crushing. For this reason, the internal series

resistance has been minimized and external high resistance

values in series with the input coupling capacitor should be

avoided. The user can exercise some control over the value

of the input time constant by introducing an external pull-up

resistance from pin 2 to the 5V supply. The maximum

voltage across the resistance will be V

less 1.5V, for black

level. For a net discharge current greater than zero, the

resistance should be greater than 450k. This will have the

effect of increasing the time constant and reducing the

degree of picture tilt. The current source I

directly tracks

reference current I

and thus increases with scan rate

adjustment, as explained later.

The signal is processed through an active 3-pole filter (F1)

designed for minimum ripple with constant phase delay. The

filter attenuates the color burst by 24dB and eliminates fast

transient spikes without sync crushing. An external filter is

not necessary. The filter also amplifies the video signal by

6dB to improve the detection accuracy. Note that the filter

cut-off frequency is a function of R

SET

through I

and is

proportional to I

Internal reference voltages (block V

REF

) with high immunity

to supply voltage variation are derived on the chip.

Reference V

with op amp A2 forces pin 6 to a reference

voltage of 1.7V nominal. Consequently, it can be seen that

the external resistance R

SET

will determine the value of the

reference current I

. The internal resistance R

is only

about 6kΩ, much less than R

SET

. All the internal timing

functions on the chip are referenced to I

and have

excellent supply voltage rejection.

Comparator C2 on the input to the sample and hold block

(S/H) compares the leading and trailing edges of the sync

pulse with a threshold voltage V

, which is referenced at a

FIGURE 12. STANDARD (NTSC INPUT) H. SYNC DETAIL

COMPOSITE SYNC OUTPUT, PIN 1

DEPENDS ON WIDTH OF INPUT SYNC AT 50% POINTS

CLAMP

INPUT

DYNAMIC

RANGE

0.5V TO 2V

BACK PORCH OUTPUT, PIN 5

SLICE

SYNC LEVEL

50%

VIDEO

100 IRE

40 IRE

SYNC

WHITE LEVEL

BLACK LEVEL

BLANKING LEVEL

SYNC TIP

COLOR BURST

40 IRE

EL4581

FN7172.2

November 12, 2010

fixed level above the clamp voltage V

. The output of C2

initiates the timing one-shots for gating the sample and hold

circuits. The sample of the sync tip is delayed by 0.8µs to

enable the actual sample of 2µs to be taken on the optimum

section of the sync. pulse tip. The acquisition time of the

circuit is about three horizontal lines. The double poly CMOS

technology enables long time constants to be achieved with

small high quality on-chip capacitors. The back porch

voltage is similarly derived from the trailing edge of sync,

which also serves to cut off the tip sample if the gate time

exceeds the tip period. Note that the sample and hold gating

times will track RSET through I

The 50% level of the sync tip is derived, through the resistor

divider R

and R

, from the sample and held voltages V

TIP

and V

, and applied to the plus input of comparator C1.

This comparator has built in hysteresis to avoid false

triggering. The output of C2 is a digital 5V signal which feeds

the C/S output buffer B1 and the other internal circuit blocks,

the vertical, back porch and odd/even functions.

The vertical circuit senses the C/S edges and initiates an

integrator which is reset by the shorter horizontal sync

pulses but times out the longer vertical sync. pulse widths.

The internal timing circuits are referenced to I

and V

the time-out period being inversely proportional to the timing

current. The vertical output pulse is started on the first

serration pulse in the vertical interval and is then self-timed

out. In the absence of a serration pulse, an internal timer will

default the start of vertical.

The back porch is triggered from the sync tip trailing edge

and initiates a one-shot pulse. The period of this pulse is

again a function of I

and will therefore track the scan rate

set by R

SET

The odd/even circuit (O/E) comprises of flip flops which track

the relationship of the horizontal pulses to the leading edge

of the vertical output, and will switch on every field at the

start of vertical. Pin 7 is high during the odd field.

Loss of video signal can be detected by monitoring the C/S

output. The 50% level of the previous video signal will

remain held on the S/H capacitors after the input video

signal has gone and the input on pin 2 has defaulted to the

clamp voltage. Consequently, the C/S output will remain low

longer than the normal vertical pulse period. An external

timing circuit could be used to detect this condition.

Block Diagram

FIGURE 13. STANDARD (NTSC INPUT) H. SYNC DETAIL

*NOTE:

RSET MUST BE A

1% RESISTOR.

C SYNC OUT

CLAMP

3-POLE FILTER

VIDEO IN

S/H

VTIP

VBP

VERTICAL

DETECT

REF

RSET

BACK

PORCH

DETECT

O/E

DETECT

ODD/EVEN

OUT

VERTICAL

OUT

GND

BURST/BACK

PORCH OUT

EL4581

FN7172.2

November 12, 2010

EL4581

Small Outline Package Family (SO)

GAUGE

PLANE

DETAIL X

4° ±4°

SEATING

PLANE

0.010 BM CA

0.004 C

0.010 BM CA

(N/2)

(N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

P1-P3 P4-P6 P7-P9 P10-P10

EL4581CSZ-T7

Mfr. #:

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Manufacturer:

Renesas / Intersil

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EL4581CSZ-T7

EL4581CSZ-T7

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