© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1 Publication Order Number:
MC14551B/D
MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally−controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
Features
• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V
DD
− V
EE
) = 3.0 to 18 V
Note: V
EE
must be v V
SS
• Linearized Transfer Characteristics
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical
• For Low R
ON
, Use The HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
• Switch Function is Break Before Make
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS
Parameter Symbol Value Unit
DC Supply Voltage Range
(Referenced to V
EE
, V
SS
≥ V
EE
)
V
DD
– 0.5 to + 18.0 V
Input or Output Voltage (DC or Transient)
(Referenced to V
SS
for Control Input and
V
EE
for Switch I/O)
V
in
, V
out
– 0.5 to V
DD
+ 0.5
V
Input Current (DC or Transient),
per Control Pin
I
in
± 10 mA
Switch Through Current I
sw
± 25 mA
Power Dissipation, per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
– 55 to + 125
_C
Storage Temperature Range T
stg
– 65 to + 150
_C
Lead Temperature (8–Second Soldering) T
L
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: − 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
for control inputs and V
EE
≤ (V
in
or V
out
)
≤ V
DD
for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14551BG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14551B
ALYWG
1
http://onsemi.com
1
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
MC14551BCP
AWLYYWWG
