DS2415
10 of 14
1-WIRE SIGNALING
The DS2415 requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read
Data. The bus master initiates all these signals, except Presence Pulse. The initialization sequence
required to begin any communication with the DS2415 is shown in Figure 8. A Reset Pulse followed by a
Presence Pulse indicates the DS2415 is ready to send or receive data given the correct ROM command
and control function command. The bus master transmits (TX) a Reset Pulse (t
RSTL
, minimum 480ms).
The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high
state via the pullup resistor. After detecting the rising edge on the data line, the DS2415 waits (t
PDH
, 15ms
to 60ms) and then transmits the Presence Pulse (t
PDL
, 60ms to 240ms).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PLUSES” Figure 8
480ms £ t
RSTL
< ¥ *
480ms £ t
RSTH
< ¥ ( INCLUDES RECOVERY TIME)
15ms £ t
PDH
< 60ms
60ms £ t
PDL
< 240ms
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always
be less than 960ms.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 9. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2415 to the master
by triggering a delay circuit in the DS2415. During write time slots, the delay circuit determines when the
DS2415 will sample the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit
determines how long the DS2415 will hold the data line low overriding the 1 generated by the master. If
the data bit is a 1, the device will leave the read data time slot unchanged.
RESISTOR
MASTER
DS2415
