DS2415
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HARDWARE CONFIGURATION Figure 6
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS2415 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol
defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling
edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of
the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire input of the DS2415 is open drain with an internal circuit equivalent
to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-
Wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approximately
5kW.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120ms, one or more of the devices on the bus may be reset. Since the DS2415 gets all its
energy for operation through its V
BAT
pin it will not perform a power-on reset if the 1-Wire bus is low for
an extended time period.
Transaction Sequence
The protocol for accessing the DS2415 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Clock Function Command
DS2415
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INITIALIZATION
All transactions on the 1-ire bus begin with an initialization sequence. The initialization sequence consists
of a Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the slave(s).
The Presence Pulse lets the bus master know that the DS2415 is on the bus and is ready to operate. For
more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in
Figure 7):
Read ROM [33h]
This command allows the bus master to read the DS2415’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS2415 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will usually result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2415 on a multidrop bus. Only the DS2415 that exactly matches the 64-bit ROM sequence
will respond to the following clock function command. All slaves that do not match the 64-bit ROM
sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the
bus.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The Search ROM process
is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
DS2415
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ROM FUNCTIONS FLOW CHART Figure 7

DS2415P+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Real Time Clock
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