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CY28419ZXCT

P1-P3P4-P6P7-P9P10-P12P13-P15
CY28419
Rev 1.0, November 22, 2006 Page 4 of 15
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge from master
.... ...................... 39:46 Data byte from slave – 8 bits
.... Data Byte (N–1) –8 bits 47 Acknowledge from master
.... Acknowledge from slave 48:55 Data byte from slave – 8 bits
.... Data Byte N –8 bits 56 Acknowledge from master
.... Acknowledge from slave .... Data byte N from slave – 8 bits
.... Stop .... Acknowledge from master
.... Stop
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
11:18 Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte from master – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read = 1
29 Acknowledge from slave
30:37 Data byte from slave – 8 bits
38 Acknowledge from master
39 Stop
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
CY28419
Rev 1.0, November 22, 2006 Page 5 of 15
Byte 0: Control Register 0
Bit @Pup Name Description
7 0 Reserved Reserved
6 1 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 1 Reserved Reserved
2 1 Reserved Reserved
1 Externally
Selected
FS_B FS_B reflects the value of the FS_B pin sampled on power-up.
0 = FS_B low at power-up
0 Externally
Selected
FS_A FS_A reflects the value of the FS_A pin sampled on power-up.
0 = FS_A low at power-up
Byte 1: Control Register 1
Bit @Pup Name Description
7 0 SRCT, SRCC Allow control of SRCT/C with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
6 1 SRCT, SRCC SRCT/C Output Enable
0 = Disabled (three-state), 1 = Enabled
5 1 Reserved Reserved
4 1 Reserved Reserved
3 1 Reserved Reserved
2 1 CPUT2, CPUC2 CPUT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
1 1 CPUT1, CPUC1 CPUT/C1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0 1 CPUT0, CPUC0 CPUT/C0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register 2
Bit @Pup Name Description
7 0 SRCT, SRCC SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
6 0 SRCT, SRCC SRCT/C Stop drive mode
0 = Driven in PCI_STP, 1 = Three-state in power-down
5 0 CPUT2, CPUC2 CPUT/C2 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
4 0 CPUT1, CPUC1 CPUT/C1 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
3 0 CPUT0, CPUC0 CPUT/C0 Pwrdwn drive mode
0 = Driven in power-down, 1 = Three-state in power-down
2 0 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
CY28419
Rev 1.0, November 22, 2006 Page 6 of 15
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 All PCI and SRC Clock outputs
except PCIF and SRC clocks
set to free-running
PCI_STP Control. 0 = SW PCI_STP not enabled and only the PCI_STP# pin will
stop the PCI stop enabled outputs, 1 = the PCI_STP function is enabled and the
stop enabled outputs will be stopped in a synchronous manner with no short pulses.
6 1 PCI6 PCI6 Output Enable
0 = Disabled, 1 = Enabled
5 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
3 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
2 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCI0 PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 USB_ 48MHz USB_48 Drive Strength
0 = High drive strength, 1 = Normal drive strength
6 1 USB_ 48MHz USB_48 Output Enable
0 = Disabled, 1 = Enabled
5 0 PCIF2 Allow control of PCIF2 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
4 0 PCIF1 Allow control of PCIF1 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
3 0 PCIF0 Allow control of PCIF0 with assertion of PCI_STP#
0 = Free Running, 1 = Stopped with PCI_STP#
2 1 PCIF2 PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit @Pup Name Description
7 1 DOT_48 DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6 1 CPUT3, CPUC3 0 = three-state, 1 = Enabled
5 0 3V66_4/VCH VCH Select 66 MHz/48 MHz
0 = 3V66 mode, 1 = VCH (48MHz) mode
4 1 3V66_4/VCH 3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3 1 3V66_3 3V66_3 Output Enable
0 = Disabled, 1 = Enabled
2 1 3V66_2 3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1 1 3V66_1 3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0 1 3V66_0 3V66_0 Output Enable
0 = Disabled, 1 = Enabled
P1-P3P4-P6P7-P9P10-P12P13-P15

CY28419ZXCT

Mfr. #:
Buy CY28419ZXCT
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner Server, CK419
Lifecycle:
New from this manufacturer.
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