OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8745BM-21LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
8745B-21 Rev D 2/17/15 1 ©2015 Integrated Device Technology, Inc.
DATA SHEET
1:1 Differential-to-LVDS Zero Delay
Clock Generator
8745B-21
General Description
The 8745B-21 is a highly versatile 1:1 LVDS Clock Generator. The
8745B-21 has a fully integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output frequency range
of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider
and Output Divider are each programmable, thereby allowing for the
following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve “zero delay”
between the input clock and the output clock. The PLL_SEL pin can
be used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL and into
the internal output dividers.
Features
• One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644
One differential feedback output pair
• Differential CLK, nCLK input pair
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: 25ps ± 125ps
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QFB
nQFB
V
DDO
SEL2
FB_IN
nFB_IN
MR
nCLK
CLK
GND
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
8745B-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Block Diagram
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q
nQ
QFB
nQFB
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
Pullup
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pin Assignment
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 2 Rev D 2/17/15
8745B-21 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
4 nFBIN Input Pullup
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
5 FBIN Input Pulldown
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
6, 15,
19, 20
SEL2, SEL3,
SEL0 SEL1
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11 V
DDO
Power Output supply pins.
8, 9 nQFB/QFB Output Differential feedback output pair. LVDS interface levels.
10, 14 GND Power Power supply ground.
12, 13 nQ/Q Output Differential output pair. LVDS interface levels.
16 V
DDA
Power Analog supply pin.
17 PLL_SEL Input Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.
18 V
DD
Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 3 Rev D 2/17/15
8745B-21 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Inputs Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q, nQ
0000 250 - 700 ÷1
0001 125 - 350 ÷1
0010 62.5 - 175 ÷1
0011 31.25 - 87.5 ÷1
0100 250 - 700 ÷2
0101 125 - 350 ÷2
0110 62.5 - 175 ÷2
0111 250 - 700 ÷4
1000 125 - 350 ÷4
1001 250 - 700 ÷8
1010 125 - 350 x2
1011 62.5 - 175 x2
1100 31.25 - 87.5 x2
1101 62.5 - 175 x4
1110 31.25 - 87.5 x4
1111 31.25 - 87.5 x8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

8745BM-21LFT

Mfr. #:
Buy 8745BM-21LFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products Differential to LVDS Zero Delay Clock Ge
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet