9FGL0241BKILF Datasheet 9FGL02P1B000KILFT, 9FGL0241BKILF, 9FGL0251BKILF | P13-P15

DECEMBER 1, 2016 13 2-OUTPUT 3.3V PCIE CLOCK GENERATOR

9FGL02 DATASHEET

SMBus Table: Stop State Control

Byte 11 Name Control Function Type 0 1 Default

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

STP[1] RW 00 = Low/Low 10 = High/Low 0

Bit 0

STP[0] RW 01 = HiZ/HiZ 11 = Low/High 0

SMBus Table: Impedance Control

Byte 12 Name Control Function Type 0 1 Default

Bit 7

DIF0_imp[1] DIF0 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 6

DIF0_imp[0] DIF0 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

SMBus Table: Impedance Control

Byte 13 Name Control Function Type 0 1 Default

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

DIF1_imp[1] DIF1 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 2

DIF1_imp[0] DIF1 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 1

X

Bit 0

X

SMBus Table: Pull-up Pull-down Control

Byte 14 Name Control Function Type 0 1 Default

Bit 7

OE0_pu/pd[1] RW 00=None 10=Pup 0

Bit 6

OE0_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

SMBus Table: Pull-up Pull-down Control

Byte 15 Name Control Function Type 0 1 Default

Bit 7

0

Bit 6

1

Bit 5

0

Bit 4

1

Bit 3

OE1_pu/pd[1] RW 00=None 10=Pup 0

Bit 2

OE1_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 1

0

Bit 0

1

Reserved

OE1 Pull-up(PuP)/

Pull-down(Pdwn) control

Reserved

See Note

Reserved

OE0 Pull-up(PuP)/

Pull-down(Pdwn) control

Reserved

True/Complement DIF Output

Disable State

See Note

Reserved

2-OUTPUT 3.3V PCIE CLOCK GENERATOR 14 DECEMBER 1, 2016

9FGL02 DATASHEET

SMBus Table: Pull-up Pull-down Control

Byte 16 Name Control Function Type 0 1 Default

Bit 7

0

Bit 6

0

Bit 5

1

Bit 4

0

Bit 3

0

Bit 2

1

Bit 1

CKPWRGD_PD_pu/pd[1] RW 00=None 10=Pup 1

Bit 0

CKPWRGD_PD_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 0

Byte 17 is Reserved

SMBus Table: Polarity Control

Byte 18 Name Control Function Type 0 1 Default

Bit 7

0

Bit 6

0

Bit 5

OE1_polarity Sets OE1 polarity RW Enabled when Low Enabled when High 0

Bit 4

0

Bit 3

OE0_polarity Sets OE0 polarity RW Enabled when Low Enabled when High 0

Bit 2

0

Bit 1

0

Bit 0

0

SMBus Table: Polarity Control

Byte 19 Name Control Function Type 0 1 Default

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

CKPWRGD_PD

Determines

CKPWRGD_PD polarity

RW

Power Down when

Low

Power Down when

High

0

Reserved

CKPWRGD_PD Pull-up(PuP)/

Pull-down(Pdwn) control

Reserved

DECEMBER 1, 2016 15 2-OUTPUT 3.3V PCIE CLOCK GENERATOR

9FGL02 DATASHEET

Recommended Crystal Characteristics (3225 package)

Marking Diagrams

Notes:

1. “LOT” is the lot sequence number.

2. “YYWW” is the last two digits of the year and week that the part was assembled.

3. Line 2: truncated part number

4. “I” denotes industrial temperature range device.

5. “P” denotes factory programmable defaults

Thermal Characteristics

PARAMETER VALUE UNITS NOTES

Frequency 25 MHz 1

Resonance Mode Fundamental

-

1

Frequency Tolerance @ 25°C

±

20 PPM Max 1

Frequency Stability, ref @ 25°C Over

Operating Temperature Range

±

20 PPM Max 1

Temperature Range (commerical) 0~70 °

C

1

Temperature Range (industrial) -40~85 °

C

1

Equivalent Series Resistance (ESR) 50

Ω

Max 1

Shunt Capacitance (C

O

)7pF Max1

Load Capacitance (C

L

)8pF Max1

Drive Level 0.3 mW Max 1

Aging per year

±5

PPM Max 1

Notes:

1. FOX 603-25-150.

LOT

241BI

YYWW

LOT

251BI

YYWW

LOT

1B000

YYWW

PARAMETER SYMBOL CONDITIONS PKG

TYP

VALUE

UNITS NOTES

θ

JC

Junction to Case 62 °

C/W

1

θ

Jb

Junction to Base 5.4 °

C/W

1

θ

JA0

Junction to Air, still air 50 °

C/W

1

θ

JA1

Junction to Air, 1 m/s air flow 43 °

C/W

1

θ

JA3

Junction to Air, 3 m/s air flow 39 °

C/W

1

θ

JA5

Junction to Air, 5 m/s air flow 38 °

C/W

1

ePad soldered to board

Thermal Resistance NLG24

9FGL0241BKILF

9FGL0241BKILF

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