DECEMBER 1, 2016 7 2-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL02 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
in
on, fast settin
1.9 2.7 4
2,3
Scope averaging, slow setting 1 2.0 3
V/ns
2,3
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 405 550 mV 1,4,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 14 140 mV 1,4,9
Avg. Clock Period Accuracy
T
PERIOD_AVG
-100 0 +2600
ppm
2,10,13
Absolute Period
T
PERIOD_ABS
Includes jitter and Spread Spectrum Modulation 9.847 10 10.203
ns
2,6
Jitter, Cycle to cycle t
c
c-c
c
37 50 ps 2,15
Voltage High V
HIGH
660 766 850 1
Voltage Low V
LOW
-150 21 150 1
Absolute Max Voltage Vmax 797 1150 1,7,15
Absolute Min Volta
e Vmin -300 -22 1,8,15
DC
Slew rate matchin
Δ
Trf 8 20
1,14
Skew, Output to Output t
sk3
Averaging on, V
T
= 50% 21 50 ps 2
2
Measured from differential waveform.
8
Defined as the minimum instantaneous volta
e includin
undershoot.
15
At default SMBus amplitude settings.
14
Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on
the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of
REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate.
1
Measured from single-ended waveform.
3
Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
6
Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread
spectrum modulation.
7
Defined as the maximum instantaneous volta
e includin
overshoot.
9
Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in
V
CROSS
for any particular system.
10
Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.
11
System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or
differential probe can be used for differential measurements. Test load CL = 2 pF.
12
T
STABLE
is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed
to droo
back into the VRB ±100 mV differential ran
e.
13
PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or
100 Hz. For 300 PPM, then we have an error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency
counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum
Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal
shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 PPM.
mV
Slew rate Trf
mV
