MAX8537EEI+ Datasheet MAX8538EEI+, MAX8537EEI+, MAX8538EEI+T | P16-P18

MAX8537/MAX8538/MAX8539

Dual-Synchronous Buck Controllers for Point-of-

Load, Tracking, and DDR Memory Power Supplies

16 ______________________________________________________________________________________

venting the output capacitor voltage from further devia-

tion from its regulating value.

Do not exceed the capacitor’s voltage or ripple

current ratings.

MOSFET Selection

The MAX8537/MAX8538/MAX8539 controllers drive two

external, logic-level, N-channel MOSFETs as the circuit-

switch elements. The key selection parameters are:

1) On-resistance (R

DS(ON)

): the lower, the better.

2) Maximum drain-to-source voltage (V

DSS

): should be

at least 20% higher than the input supply rail at the

high-side MOSFET’s drain.

3) Gate charges (Q

, Q

): the lower, the better.

Choose MOSFETs with R

DS(ON)

rated at V

= 4.5V. For

a good compromise between efficiency and cost,

choose the high-side MOSFET that has conduction loss

equal to the switching loss at the nominal input voltage

and maximum output current. For the low-side MOSFET,

make sure it does not spuriously turn on due to dV/dt

caused by the high-side MOSFET turning on, as this

results in shoot-through current degrading the efficiency.

MOSFETs with a lower Q

ratio have higher immu-

nity to dV/dt.

For proper thermal-management design, the power dis-

sipation must be calculated at the desired maximum

operating junction temperature, maximum output cur-

rent, and worst-case input voltage (for low-side

MOSFET, worst case is at V

IN(MAX)

; for high-side

MOSFET, it could be either at V

IN(MIN)

or V

IN(MAX)

High-side and low-side MOSFETs have different loss

components due to the circuit operation. The low-side

MOSFET, operates as a zero-voltage switch; therefore,

the major losses are the channel conduction loss

LSCC

) and the body-diode conduction loss (P

LSDC

LSCC

= [1 - (V

OUT

/ V

)] x (I

LOAD

)

x R

DS,ON

Use R

DS,ON

at T

J(MAX)

LSDC

= 2 x I

LOAD

x V

x t

x f

where V

is the body-diode forward voltage drop, t

the dead-time between the high-side MOSFET and the

low-side MOSFET switching transitions, and f

is the

switching frequency.

The high-side MOSFET operates as a duty-cycle control

switch and has the following major losses: the channel

conduction loss (P

HSCC

), the V I overlapping switching

loss (P

HSSW

), and the drive loss (P

HSDR

). The high-side

MOSFET does not have body-diode conduction loss

because the diode never conducts current.

HSCC

= (V

OUT

/ V

) x I

LOAD

x R

DS(ON)

Use R

DS(ON)

at T

J(MAX):

HSSW

= V

x I

LOAD

x f

x [(Q

+ Q

) / I

GATE

]

where I

GATE

is the average DH-high driver output-

current capability determined by:

GATE(ON)

= 2.5 / (R

+ R

GATE

)

where R

is the high-side MOSFET driver’s average

on-resistance (1.1Ω typ) and R

GATE

is the internal gate

resistance of the MOSFET (~2Ω):

HSDR

= Q

x V

x f

x R

GATE

/ (R

GATE

+ R

)

where V

~ VL = 5V

In addition to the losses above, approximately 20% more

for additional losses due to MOSFET output capaci-

tances and low-side MOSFET body-diode reverse-recov-

ery charge dissipated in the high-side MOSFET that

exists, but is not well defined in the MOSFET data sheet.

Refer to the MOSFET data sheet for thermal-resistance

specification to calculate the PC board area needed to

maintain the desired maximum operating junction tem-

perature with the above-calculated power dissipation.

To reduce EMI caused by switching noise, add a 0.1µF

ceramic capacitor from the high-side switch drain to

the low-side switch source or add resistors in series

with DH and DL to slow down the switching transitions.

However, adding series resistors increases the power

dissipation of the MOSFETs, so be sure this does not

overheat the MOSFETs.

The minimum load current must exceed the high-side

MOSFET’s maximum leakage current over temperature

if fault conditions are expected.

Current-Limit Setting

The MAX8537/MAX8538/MAX8539 controllers sense

the peak inductor current to provide constant current

and hiccup current limit. The peak current-limit thresh-

old is set by an external resistor together with the inter-

nal current sink of 200µA. The voltage drop across the

resistor R

ILIM_

with 200µA current through it sets the

maximum peak inductor current that can flow through

the high-side MOSFET or the optional current-sense

resistor by the equations below:

PEAK(MAX)

= 200µA x R

ILIM_

/ R

DSON(HSFET)

PEAK(MAX)

= 200µA x R

ILIM_

/ R

SENSE

ILIM_

should be less than 1.5kΩ for optimum current-

limit accuracy. The actual corresponding maximum

load current is lower than the I

PEAK(MAX)

above by half

MAX8537/MAX8538/MAX8539

Dual-Synchronous Buck Controllers for Point-of-

Load, Tracking, and DDR Memory Power Supplies

______________________________________________________________________________________ 17

of the inductor ripple current (see the Inductor

Selection section). If R

DS(ON)

of the high-side MOSFET

is used for current sensing, make sure to use the maxi-

mum R

DS(ON)

at the highest operating junction temper-

ature to avoid fault tripping of the current limit at

elevated temperature. Consideration should also be

given to the tolerance of the 200µA current sink.

When R

DS(ON)

of the high-side MOSFET is used for cur-

rent sensing, ringing on the LX voltage waveform can

interfere with the current limit. Below is the procedure for

selecting the value of the series RC snubber circuit:

1) Connect a scope probe to measure V

to GND,

and observe the ringing frequency, f

2) Find the capacitor value (connected from LX to

GND) that reduces the ringing frequency by half.

The circuit parasitic capacitance (C

PAR

) at LX is

then equal to 1/3rd the value of the added capaci-

tance above. The circuit parasitic inductance (L

PAR

)

is calculated by:

The resistor for critical dampening (R

SNUB

) is equal to 2π

x f

x L

PAR

. Adjust the resistor value up or down to tailor

the desired damping and the peak voltage excursion.

The capacitor (C

SNUB

) should be at least 2 to 4 times

the value of the C

PAR

in order to be effective. The

power loss of the snubber circuit is dissipated in the

resistor (P

RSNUB

) and can be calculated as:

where V

is the input voltage and f

is the switching

frequency. Choose an R

SNUB

power rating that meets

the specific application’s derating rule for the power

dissipation calculated.

Additionally, there is parasitic inductance of the cur-

rent-sensing element, whether the high-side MOSFET

DS(ON)

SENSE_FET

) or the actual current-sense

resistor R

SENSE

RSENSE

) are used, which is in series

with the output filter inductor. This parasitic inductance,

together with the output inductor, form an inductive

divider and cause error in the current-sensing voltage.

To compensate for this error, a series RC circuit can be

added in parallel with the sensing element (see Figure

1). The RC time constant should equal L

RSENSE

SENSE

, or L

SENSE_FET

/ R

DS(ON)

. First, set the value of

R equal to or less than R

ILIM_

/ 100. Then, the value of

C can be calculated as:

C = L

RSENSE

/ (R

SENSE

x R) or

C = L

SENSE_FET

/ (R

DS(ON)

x R)

Any PC board trace inductance in series with the sens-

ing element and output inductor should be added to

the specified FET or resistor inductance per the

respective manufacturer’s data sheet. For the case of

the MOSFET, it is the inductance from the drain to the

source lead.

An additional switching noise filter may be needed at

ILIM_ by connecting a capacitor in parallel with R

ILIM_

(in the case of R

DS(ON)

sensing) or from ILIM_ to LX (in

the case of resistor sensing). For the case of R

DS(ON)

sensing, the value of the capacitor should be:

C > 50 / (3.1412 x f

x R

ILIM_

)

For the case of resistor sensing:

C < 25 x 10

-9

/ R

ILIM_

Soft-Start Capacitor Setting

The two step-down converters have independent,

adjustable soft-start. External capacitors from SS1/SS2

to ground are charged by an internal 5µA current

source to the corresponding feedback threshold.

Therefore, the soft-start time can be calculated as:

= C

x V

/ 5µA

For example, 0.01µF from SS1 to ground corresponds

to approximately a 1.6ms soft-start period for step-

down 1.

Compensation Design

The MAX8537/MAX8538/MAX8539 use a voltage-mode

control scheme that regulates the output voltage by

comparing the error-amplifier output (COMP) with a

fixed internal ramp to produce the required duty cycle.

The error amplifier is an operational amplifier with

25MHz bandwidth to provide fast response. The output

lowpass LC filter creates a double pole at the resonant

frequency that introduces a gain drop of 40dB per

decade and a phase shift of 180 degrees per decade.

The error amplifier must compensate for this gain drop

and phase shift to achieve a stable high-bandwidth

closed-loop system.

The basic regulator loop can be thought of as consist-

ing of a power modulator and an error amplifier. The

power modulator has DC gain set by V

/ V

RAMP

, with

a double pole, f

P_LC

, and a single zero, f

Z_ESR

, set by

the output inductor (L), the output capacitor (C

), and

its equivalent series resistance (R

ESR

). Below are the

equations that define the power modulator:

PCVf

RSNUB SNUB IN SW

=×

()

PAR

R PAR

()

MAX8537/MAX8538/MAX8539

Dual-Synchronous Buck Controllers for Point-of-

Load, Tracking, and DDR Memory Power Supplies

18 ______________________________________________________________________________________

When the output capacitor is composed of paralleling n

number of the same capacitors, then:

Thus, the resulting f

Z_ESR

is the same as that of a sin-

gle capacitor.

The total closed-loop gain must be equal to unity at the

crossover frequency, where the crossover frequency is

less than or equal to 1/5th the switching frequency (f

≤ f

/ 5

So the loop-gain equation at the crossover frequency is:

EA(FC)

x G

MOD(FC)

= 1

where G

EA(FC)

is the error-amplifier gain at f

, and

MOD(FC)

is the power-modulator gain at f

The loop compensation is affected by the choice of out-

put filter capacitor due to the position of its ESR-zero fre-

quency with respect to the desired closed-loop crossover

frequency. Ceramic capacitors are used for higher

switching frequencies (above 750kHz) and have low

capacitance and low ESR; therefore, the ESR-zero fre-

quency is higher than the closed-loop crossover frequen-

cy. Electrolytic capacitors (e.g., tantalum, solid polymer,

and OS-CON) are needed for lower switching frequen-

cies and have high capacitance and higher ESR; there-

fore, the ESR-zero frequency is lower than the

closed-loop crossover frequency. Thus, the compensa-

tion design procedures are separated into two cases:

Case 1: Crossover frequency is less than the output-

capacitor ESR-zero (f

< f

Z_ESR

The modulator gain at f

is:

MOD(FC)

= G

MOD(DC)

x (f

P_LC

/ f

)

Since the crossover frequency is lower than the output

capacitor ESR-zero frequency and higher than the LC

double-pole frequency, the error-amplifier gain must

have a +1 slope at f

so that, together with the -2 slope

of the LC double pole, the loop crosses over at the

desired -1 slope.

The error amplifier has a dominant pole at a very low

frequency (~0Hz), and two additional zeros and two

additional poles as indicated by the equations below

and illustrated in Figure 6:

Z1_EA

= 1 / (2π x R4 x C2)

Z2_EA

= 1 / (2π x (R1 + R3) x C1)

P2_EA

= 1 / (2π x R3 x C1)

P3_EA

= 1 / (2π x R4 x (C2 x C3 / (C2 + C3)))

Note that f

Z2_EA

and f

P2_EA

are chosen to have the

converter closed-loop crossover frequency, f

, occur

when the error-amplifier gain has +1 slope, between

Z2_EA

and f

P2_EA

. The error-amplifier gain at f

must

meet the requirement below:

EA(FC)

= 1 / G

MOD(FC)

The gain of the error amplifier between f

Z1_EA

and

Z2_EA

is:

Z1_EA

- f

Z2_EA

) = G

EA(FC)

x f

Z2_EA

/ f

Z2_EA

/ (f

x G

MOD(FC)

)

This gain is set by the ratio of R4/R1, where R1 is calcu-

lated in the Output Voltage Setting section. Thus:

R4 = R1 x f

Z2_EA

/ (f

x G

MOD(FC)

)

where f

Z2_EA

= f

P_LC

Due to the underdamped (Q > 1) nature of the output

LC double pole, the first error-amplifier zero frequency

must be set less than the LC double-pole frequency in

order to provide adequate phase boost. Set the error-

amplifier first zero, f

Z1_EA

, at 1/4th the LC double-pole

frequency. Hence:

C2 = 2 / (π x R4 x f

P_LC

)

Set the error amplifier f

P2_EA

at f

Z_ESR

and f

P3_EA

equal

to half the switching frequency. The error-amplifier gain

between f

P2_EA

and f

P3_EA

is set by the ratio of R4/R

and is equal to:

Z1_EA

- f

Z2_EA

) x (f

Z_ESR

/ f

P_LC

)

where R

= R1 x R3 / (R1 + R3). Then:

= R4 x f

P_LC

/ (G

Z1_EA

- f

Z2_EA

) x f

Z_ESR

) =

R4 x f

x G

MOD(FC)

/ f

Z_ESR

The value of R3 can then be calculated as:

R3 = R1 x R

/ (R1 – R

)

Now we can calculate the value of C1 as:

C1 = 1 / (2π x R3 x f

Z_ESR

)

and C3 as:

C3 = C2 / ((2π x C2 x R4 x f

P3_EA

) - 1)

CnC

and

O EACH

ESR

ESR EACH

=×

where V V typ

MOD DC

RAMP

PLC

Z ESR

ESR O

()

,()

××

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MAX8537EEI+

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Switching Controllers Dual-Synchronous Buck Controller

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