NCP5201
http://onsemi.com
7
VDDQ Regulator in Standby Mode (S3)
An internal P−Channel power FET switching at 500 kHz
(doubled frequency), with peak current limit preset at
2.0 A, provides nonsynchronous switch−mode control
while in the S3 state. In this mode, the internal P−Channel
power FET derives its source from the 5 VSTBY pin. The
2.0 A peak current limit is designed to yield an average
output current limit of 700 mA when using a 1.7 H output
inductor. When using this value inductor, the regulator will
operate in discontinuous conduction mode (DCM) in the S3
state. And, switching in doubled frequency (500 kHz) is to
reduce the peak conduction current. In this operating mode,
the body diode of the external synchronous MOSFET acts
as a flywheel diode and the MOSFET is never turned on.
TGDDQ and BGDDQ are set Low to disable the external
switches. Nominal output voltage and the PWM control
scheme of Normal mode still apply.
Table 2. States, Operation and Output Pin Conditions
Operation Mode
Operating Conditions Output Pin Conditions
VDDQ VTT TGDDQ BGDDQ PWRGD
S0 Normal Normal Normal Normal H−Z
S3 Standby H−Z Low Low Low
S5 H−Z H−Z Low Low Low
Fault Protection of VDDQ Regulator
During state S0, external resistor (RL1) sets current limit
for the high−side switch. An internal 10 A current sink at
pin OCDDQ establishes the voltage drop across this
resistor, which is compared to the voltage at the SDDQ pin
when the high−side drive is high, and after a fixed period
(500 ns) of blanking time to avoid false current limit
triggering. When the voltage at SDDQ is lower than that at
OCDDQ, an overcurrent condition occurs, both FETs are
latched−off until the IC goes into S5 then S0, VDDQ will
soft−start again. This protects against a short−to−ground
condition on SDDQ or VDDQ.
During state S3, the internal P−Channel power FET is
activated and switching. If the conduction current of the
FET is higher than 2.0 A after a fixed period (X500 ns) of
blanking time, an overcurrent condition occurs, and the
FET is turned off for the remainder of that switching cycle.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 1.
VTT Active Terminator in Normal Mode (S0)
The VTT regulator is a two−quadrant linear regulator
with internal N−channel power FETs to provide transient
current sink and source capability up to 1.8 A. This output
is activated in normal mode in state S0 when VDDQ is in
regulation. It is in standby mode in state S3. When in
normal mode and VTT is in regulation, signal INREGVTT
will go HIGH to notify the control logic block. The input
power path is from VDDQ. Gate drive power is derived
from VSTBY. VTT is stable with any value of output
capacitor greater than 220 F, and is insensitive to ESR
value ranging 2 m to 400 m.
VTT Active Terminator in Standby Mode (S3)
VTT output is high−impedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional
current limit is implemented, preset at 2.3 A magnitude.
Thermal Consideration of VTT Active Terminator
The VTT terminator is designed to handle large transient
output currents. If large currents are required for very long
durations, then care should be taken to ensure the
maximum junction temperature is not exceeded. The 5 × 6
QFN−18 has a thermal resistance 35°C/W (dependent on
air flow, grade of copper and number of VIAs).
Undervoltage Monitor
The IC monitors VSTBY and VCC. If VSTBY is higher
than its preset threshold (derived from VREF, with
hysteresis), _VSTGD is set HIGH. Operation is identical
for VCC and _12 VGD. The CONTROL LOGIC accepts
both _VSTGD and _12 VGD to determine the state of the
IC.
