NCP1216, NCP1216A
http://onsemi.com
12
315.4U 882.7U 1.450M 2.017M 2.585M
300
200
100
0
Figure 23. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise Free Operation
Skip Cycle
Current Limit
Max Peak
Current
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 24 depicts the application example:
Figure 24. Another Way of Shutting Down the IC
without a Definitive Latchoff State
8
7
6
5
1
2
3
4
Q1
ON/OFF
A full latching shutdown, including overtemperature
protection, is described in application note AND8069/D.
Power Dissipation
The NCP1216 is directly supplied from the DC rail
through the internal DSS circuitry. The current flowing
through the DSS is therefore the direct image of the
NCP1216 current consumption. The total power dissipation
can be evaluated using:
(V
HVDC
* 11 V) I
CC2
(eq. 10)
which is, as we saw, directly related to the MOSFET Q
g
. If
we operate the device on a 90−250 VAC rail, the maximum
rectified voltage can go up to 350 VDC. However, as the
characterization curves show, the current consumption
drops at a higher junction temperature, which quickly occurs
due to the DSS operation. In our example, at
T
ambient
= 50°C, I
CC2
is measured to be 2.9 mA with a
10 A / 600 V MOSFET. As a result, the NCP1216 will
dissipate from a 250 VAC network,
350 V 2.9 mA@T
A
+ 50 C + 1W
(eq. 11)
°
The PDIP−7 package offers a junction−to−ambient thermal
resistance R
qJ−A
of 100°C/W. Adding some copper area
around the PCB footprint will help decreasing this number:
12 mm x 12 mm to drop R
qJ−A
down to 75°C/W with 35 m
copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m
copper thickness (2 oz.). For a SOIC−8, the original
178°C/W will drop to 100°C/W with the same amount of
copper. With this later PDIP−7 number, we can compute the
maximum power dissipation that the package accepts at an
ambient of 50°C:
P
max
+
T
Jmax
* T
Amax
R
qJ * A
+ 1W
(eq. 12)
which barely matches our previous budget. Several
solutions exist to help improving the situation:
1. Insert a Resistor in Series with Pin 8: This resistor will
take a part of the heat normally dissipated by the NCP1216.
Calculations of this resistor imply that V
pin8
does not drop
below 30 V in the lowest mains conditions. Therefore, R
drop
can be selected with:
R
drop
v
V
bulkmin
* 50 V
8mA
(eq. 13)
In our case, V
bulk
minimum is 120 VDC, which leads to a
dropping resistor of 8.7 kW. With the above example in
mind, the DSS will exhibit a duty−cycle of:
2.9 mAń8mA+ 36%
(eq. 14)
By inserting the 8.7 kW resistor, we drop
8.7 kW *8mA+ 69.6 V
(eq. 15)
during the DSS activation. The power dissipated by the
NCP1216 is therefore:
P
instant
*DSS
duty * cycle
+
(eq. 16)
(350 * 69) * 8 m * 0.36 + 800 mW
We can pass the limit and the resistor will dissipate
(eq. 17)
1W* 800 mW + 200 mW
or
(eq. 18)
p
drop
+
69
2
8.7 k
*0.36
2. Select a MOSFET with a Lower Q
g
: Certain MOSFETs
exhibit different total gate charges depending on the
technology they use. Careful selection of this component
can help to significantly decrease the dissipated heat.
3. Implement Figure 3, from AN8069/D, Solution: This is
another possible option to keep the DSS functionality (good
short−circuit protection and EMI jittering) while driving any
types of MOSFETs. This solution is recommended when the
designer plans to use SOIC−8 controllers.
