NCP1216, NCP1216A
http://onsemi.com
13
4. Connect an Auxiliary Winding: If the mains conditions
are such that you simply can’t match the maximum power
dissipation, then you need to connect an auxiliary winding
to permanently disconnect the startup source.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1216
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty−cycle. The system auto−recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the V
CC
decoupling capacitor: as soon as the
V
CC
decreases from the VCC
OFF
level (typically 12.2 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC
ON
level is
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 350 mA typical (I
CC3
parameter). As a result, the V
CC
level slowly discharges
toward 0 V. When this level crosses 5.6 V typical, the
controller enters a new startup phase by turning the current
source on: V
CC
rises toward 12.2 V and again delivers
output pulses at the VCC
OFF
crossing point. If the fault
condition has been removed before VCC
ON
approaches,
then the IC continues its normal operation. Otherwise, a new
fault cycle takes place. Figure 25 shows the evolution of the
signals in presence of a fault.
Figure 25.
Latchoff
Phase
Time
Time
Time
Fault is
Relaxed
Regulation
Occurs Here
V
CC
12.2 V
10 V
5.6 V
Fault Occurs Here
Startup Phase
Internal
Fault Flag
Driver
Pulses
Drv
Driver
Pulses
VCC
OFF
= 12.2 V
VCC
ON
= 10 V
VCC
latch
= 5.6 V
If the fault is relaxed during the V
CC
natural fall down
sequence, the IC automatically resumes.
If the fault still persists when V
CC
reached VCC
ON
, then the
controller cuts everything off until recovery.
Calculating the VCC Capacitor
As the above section describes, the fall down sequence
depends upon the V
CC
level: how long does it take for the
V
CC
line to go from 12.2 V to 10 V. The required time
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a V
CC
fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
NCP1216, NCP1216A
http://onsemi.com
14
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
Dt +
DV·C
i
(eq. 19)
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at V
CC
= 10 V and it remains
stuck until V
CC
reaches 5.6 V: we are in latchoff phase.
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designers duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between V
CC
and GND. If the current sense pin is
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its V
CC
capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by R
sense
. Unfortunately, if the quality
coefficient Q of the resonating network formed by L
p
and
C
bulk
is low (e.g. the MOSFET R
dson
+ R
sense
are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its V
CC
capacitor. If this V
CC
capacitor is of sufficient value,
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal V
CC
discharge testifies for latchup.
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence
V
CC
5 V/DIV
10 ms/DIV
V
latch
1 V/DIV
0
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (−2 * V
f
) due to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
Another option (Figure 28) consists in wiring a diode
from V
CC
to the bulk capacitor to force V
CC
to reach
VCC
ON
sooner and thus stops the switching activity before
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
NCP1216, NCP1216A
http://onsemi.com
15
Figure 27. Figure 28.
A simple resistor in series avoids any latchup in the controller
or one diode forces V
CC
to reach V
CCON
sooner.
D3
1N400
7
1
2
45
8
6
7
3
+
+
CV
CC
C
bulk
1
2
45
8
6
7
3
+
+
CV
CC
C
bulk
R
bulk
> 4.7 k
Soft−StartNCP1216A only
The NCP1216A features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
V
CC
reaches V
CCOFF
, the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). This situation lasts during 1ms and further
to that time period, the peak current limit is blocked to
1.0 V until the supply enters regulation. The soft−start is also
activated during the over current burst (OCP) sequence.
Every restart attempt is followed by a soft−start activation.
Generally speaking, the soft−start will be activated when
V
CC
ramps up either from zero (fresh power−on sequence)
or 5.6 V, the latchoff voltage occurring during OCP.
Figure 29 portrays the soft−start behavior. The time scales
are purposely shifted to offer a better zoom portion.
Figure 29. Soft−start is activated during a startup sequence or an OCP condition

NCP1216AD100R2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTRLR PWM CM OTP HV 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union