M53015 Evaluation Board, Rev. 0.5
10 Freescale Semiconductor
5.19 I2C
The I2C bus of the MCF53015 is used in several places on the M53015EVB. It is connected to a serial
EEPROM, a USB OTG Charge Pump, and a programmable clock generator. These pins are also accessible
on the University Breakout Connector, J1. Table 3 below defines the device addresses for the devices
connected to the I2C bus.
Table 9. I2C Device Addresses
5.20 eSDHC
The MCF53015 features an Enhanced Secure Digital Host Controller (eSDHC) that supports CE-ATA,
SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMC plus, and MMC. The
M53015EVB provides an MMC/SD connector to evaluate the features of the eSDHC.
5.21 Power Regulation
The M53015EVB uses Freescale Switch-Mode power supplies to generate on-board voltages from a single
external 5V supply. The Dual MC34717 generates 1.8V for the memory subsystems and 1.2V to power
the MCF53015 core. The single MC34713 generates 3.3V to power on-board devices. The external 5V
supply is provided through a barrel jack connector, J51. A power switch, SW6, is provided to turn power
to the board off.
Jumpers are provided that allow for the 3.3V, 1.8V, and 1.2V supplies to be separated from the
MCF53015. The intention of these jumpers is to connect a current meter to measure the power consumed
by the MCF53015 processor.
Table 8. UART0 Configuration
Function J44 J45
Communicate with UART0 through the Serial to USB
bridge connector, J49
2-3 2-3
Device Address
Serial EEPROM XXX
USB OTG Charge Pump XXX
Programmable Clock Generator XXX
M53015 Evaluation Board, Rev. 0.5
Freescale Semiconductor 11
5.22 Boot Options
The MCF53015 has three boot options:
Boot from FlexBus with defaults, unified SDR bus/FlexBus
Boot from FlexBus with defaults, split DDR bus/FlexBus
Boot from FlexBus and override defaults via address bus (FB_A[21:17])
The boot mode is determined by the BOOTMOD[1:0] inputs into the MCF53015. The mode switches
(SW4[2:1]) control the BOOTMOD[1:0] inputs to the MCF53015.
When booting from FlexBus with overrides from the data bus, the SW6 and SW7 settings control the state
of FB_AD[7:0] during reset (while /RSTOUT is asserted). The following table describes the override
settings.
Table 10. SW3, SW4, and SW5 Settings
Pins Affected Switch Settings
1
Function
(none)
SW4-1/SW4-2 Boot Mode
OFF/OFF Boot from FlexBus with defaults, unified SDR bus/FlexBus
OFF/ON
Boot from FlexBus with defaults, split DDR bus/FlexBus
ON/OFF Boot from FlexBus and override defaults via address bus (FB_A[21:17])
ON/ON Reserved
A16
SW5-1 Master Mode
ON Master Mode
OFF Reserved
A17
SW5-2 SDRAM/FlexBus Mode
ON SDR mode (unified data bus)
OFF DDR mode (split data bus)
A18
SW5-3 Oscillator Mode
ON Oscillator bypass mode
OFF Crystal oscillator mode
A19
SW5-4 Load
ON High drive strength (50 pF)
OFF Low drive strength (20 pF)
A20
SW3-1 Boot Port Size
ON 8-bit for split bus or 32-bit for unified bus
OFF 16-bit split or unified bus
M53015 Evaluation Board, Rev. 0.5
12 Freescale Semiconductor
5.23 Jumpers, Headers, and Switches
Headers and jumpers on the M53015EVB allow for user control of the hardware configuration. The
following tables provide descriptions for each of these settings:
A21
SW3-2 Chip Select Configuration
ON FB_A[23:22] = FB_A[23:22]
OFF FB_A[23:22] = FB_CS[3:2]
A22
SW3-3 Reserved
ON Reserved
OFF Default
1
Bold indicates the default setting, SW4-3, SW4-4, and SW3-4 are not connected and their position does not affect
configuration.
Table 11. Header Settings
Reference Designator Setting
1,2
Function
H1
ON Connects a 4 ohm load across the SPKR_N and SPKR_P lines of the internal CODEC
OFF Disconnects the 4 ohm load across the SPKR_N and SPKR_P lines of the internal CODEC
H2
ON Connects the T0IN line to the LED D1
OFF Disconnects the T0IN line from the LED D1
H3
ON Connects the T1IN line to the LED D2
OFF Disconnects the T1IN line from the LED D2
H4
ON Connects the T2IN line to the LED D3
OFF Disconnects the T2IN line from the LED D3
H5
ON Connects the T3IN line to the LED D4
OFF Disconnects the T3IN line from the LED D4
H6
ON Grounds the ADC_N/MIC_N line of the internal CODEC to AVSS_SPKR_HP_HDST
OFF Disconnects the ADC_N/MIC_N line of the internal CODEC from AVSS_SPKR_HP_HDST
H7
ON
Connects the Left channel of the Speaker/Headphone Out jack (J18) to the speaker lines
(for speaker use)
OFF
Disconnects the Left channel of the Speaker/Headphone Out jack (J18) from the speaker
lines (for Headphone Out use)
H8
1-2 Adds a 1.0uF capacitor in series with the ADC_N/MIC_N line of the internal CODEC
3-4 Adds a 0.1uF capacitor in series with the ADC_N/MIC_N line of the internal CODEC
5-6 Removes in series capacitance from the ADC_N/MIC_N line of the internal CODEC
Table 10. SW3, SW4, and SW5 Settings (continued)
Pins Affected Switch Settings
1
Function

M53015EVB

Mfr. #:
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NXP / Freescale
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Development Boards & Kits - COLDFIRE EVAL BD FOR M53107
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