© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 10
1 Publication Order Number:
NB100LVEP221/D
NB100LVEP221
2.5V/3.3V 2:1:20
Differential HSTL/ECL/PECL
Clock Driver
Description
The NB100LVEP221 is a low skew 2:1:20 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1
can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
single−ended (if the V
BB
output is used).
The LVEP221 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50 W even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive V
CC
supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The V
BB
pin, an internally generated voltage supply, is available to this
device only. For single−ended LVPECL input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
Single−ended CLK input operation is limited to a V
CC
≥ 3.0 V in
LVPECL mode, or V
EE
≤ −3.0 V in NECL mode.
Features
• 15 ps Typical Output−to−Output Skew
• 40 ps Typical Device−to−Device Skew
• Jitter Less than 2 ps RMS
• Maximum Frequency > 1.0 GHz Typical
• Thermally Enhanced 52−Lead LQFP and QFN
• V
BB
Output
• 540 ps Typical Propagation Delay
• LVPECL and HSTL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −2.375 V to −3.8 V
• Q Output will Default Low with Inputs Open or at V
EE
• Pin Compatible with Motorola MC100EP221
• These Devices are Pb−Free and are RoHS Compliant
LQFP−52
FA SUFFIX
CASE 848H
MARKING
DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
NB100
LVEP221
AWLYYWWG
1
QFN−52
MN SUFFIX
CASE 485M
152
NB100
LVEP221
AWLYYWWG
1
52
52
