15
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
Figure 9. Timing for
AEAE
AEAE
AE
when FIFO is Almost-Empty
Figure 8. IR Flag Timing and First Available Write when the FIFO is Full
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
CSB
OR
W/RB
MBB
ENB
B0 - B35
CLKB
IR
CLKA
CSA
W/RA
A0 - A35
MBA
ENA
4658 drw 11
12
t
CLK
t
CLKH
t
CLKL
t
ENS1
t
ENH1
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
PIR
t
PIR
t
ENS2
t
ENS1
t
DS
t
ENH2
t
ENH1
t
DH
Previous Word in FIFO Output Register
Next Word From FIFO
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO Full
Write
AE
CLKA
ENB
ENA
CLKB
4658 drw 12
2
1
t
ENS1
t
ENH1
t
SKEW2
t
PAE
t
PAE
t
ENS1
t
ENH1
X Word in FIFO
(X+1) Words in FIFO
(1)
