8
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
is complete, the X and Y register values are loaded bitwise through the FS0/
SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is
LOW. There are 18- or 20-bit writes needed to complete the programming for
the IDT72V3631 or IDT72V3641 respectively. The first-bit write stores the most
significant bit of the Y register, and the last-bit write stores the least significant bit
of the X register. Each register value can be programmed from 1 to 508
(IDT72V3631) or 1 to 1,020 (IDT72V3641).
When the option to program the Offset registers serially is chosen, the Input
Ready (IR) flag remains LOW until all register bits are written. The IR flag is set
HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow
normal FIFO operation. The timing diagram for serial load of offset registers
can be found in Figure 4.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-A Chip
Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA and the port-A Mailbox select (MBA) are LOW,
W/RA, the port-A Enable (ENA), and the Input Ready (IR) flag are HIGH (see
Table 2). Writes to the FIFO are independent of any concurrent FIFO read.
For the Write Cycle Timing diagram, see Figure 5.
The port-B control signals are identical to those of port-A with the exception
that the port-B Write/Read select (W/RB) is the inverse of the port-A Write/Read
select (W/RA). The state of the port-B data (B0-B35) outputs is controlled by
the port-B Chip Select (CSB) and the port-B Write/Read select (W/RB). The
B0-B35 outputs are in the high-impedance state when either CSB is HIGH or
W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB
is HIGH.
Data is read from the FIFO to its output register on a LOW-to-HIGH transition
of CLKB when CSB and the port-B Mailbox select (MBB) are LOW, W/RB, the
port-B Enable (ENB), and the Output Ready (OR) flag are HIGH (see Table
3). Reads from the FIFO are independent of any concurrent FIFO writes. For
the Read Cycle Timing diagram, see Figure 6.
The setup- and hold-time constraints to the port clocks for the port Chip Selects
and Write/Read selects are only for enabling write and read operations and are
not related to high-impedance control of the data outputs. If a port Enable is LOW
during a clock cycle, the port Chip Select and Write/Read select may change
states during the setup- and hold time window of the cycle.
When the OR flag is LOW, the next data word is sent to the FIFO output register
automatically by the CLKB LOW-to-HIGH transition that sets the OR flag HIGH.
When OR is HIGH, an available data word is clocked to the FIFO output register
only when a FIFO read is selected by the port-B Chip Select (CSB), Write/Read
select (W/RB), Enable (ENB), and Mailbox select (MBB).
SIGNAL DESCRIPTION
RESET
The IDT72V3631/72V3641
is reset by taking the Reset (RST) input LOW
for at least four port-A Clock (CLKA) and four port-B (CLKB) LOW-to-HIGH
transitions. The Reset input may switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the Input Ready (IR)
flag LOW, the Output Ready (OR) flag LOW, the Almost-Empty (AE) flag LOW,
and the Almost-Full (AF) flag HIGH. Resetting the device also forces the Mailbox
Flags (MBF1, MBF2) HIGH. After a FIFO is reset, its Input Ready flag is set
HIGH after at least two clock cycles to begin normal operation. A FIFO must be
reset after power up before data is written to its memory. The relevant FIFO
Reset timing diagram can be found in Figure 2.
FIRST WORD FALL THROUGH MODE (FWFT)
These devices operate in the First Word Fall Through mode (FWFT). This
mode uses the Output Ready function (OR) to indicate whether or not there is
valid data at the data outputs (B0-B35). It also uses the Input Ready (IR) function
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAM-
MING
Two registers in these devices are used to hold the offset values for the Almost-
Empty and Almost-Full flags. The Almost-Empty (AE) flag Offset register is
labeled X, and the Almost-Full (AF) flag Offset register is labeled Y. The Offset
register can be loaded with a value in three ways: one of two preset values are
loaded into the Offset registers, parallel load from port A, or serial load. The Offset
register programming mode is chosen by the flag select (FS1, FS0) inputs during
a LOW-to-HIGH transition on the RST input (See Table 1).
— PRESET VALUES
If the preset value of 8 or 64 is chosen by the FS1 and FS0 inputs at the time
of a RST LOW-to-HIGH transition according to Table 1, the preset value is
automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set HIGH after two LOW-
to-HIGH transitions on CLKA. For the Preset value loading timing diagram, see
Figure 2.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from port A, the device is reset with FS0
and FS1 LOW during the LOW-to-HIGH transition of RST. After this reset is
complete, the IR flag is set HIGH after two LOW-to-HIGH transitions on CLKA.
The first two writes to the FIFO do not store data in its memory but load the Offset
registers in the order Y, X. Each Offset register of the IDT72V3631 and
IDT72V3641 uses port-A inputs (A8-A0), (A9-A0), and (A10-A0), respec-
tively. The highest number input is used as the most significant bit of the binary
number in each case. Each register value can be programmed from 1 to 508
(IDT72V3631) and 1 to 1,020 (IDT72V3641). After both Offset registers are
programmed from port A, subsequent FIFO writes store data in the RAM. The
timing diagram for parallel load of offset registers can be found in Figure 3.
— SERIAL LOAD
To program the X and Y registers serially, the device is reset with FS0/SD
and FS1/SEN HIGH during the LOW-to-HIGH transition of RST. After this reset
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
FS1 FS0 RST X and Y Registers
(1)
HH↑ Serial Load
HL↑ 64
LH↑ 8
LL↑ Parallel Load From Port A
TABLE 1
— —
— —
— FLAG PROGRAMMING
