Philips Semiconductors Product data
74F240Octal inverting buffer
2
2004 Feb 25
FEATURES
• Octal bus interface
• 3-state buffer outputs sink 64 mA
• 15 mA source current
DESCRIPTION
The 74F240 is an octal inverting buffer that is ideal for driving bus
lines of buffer memory address registers. The outputs are all
capable of sinking 64 mA and sourcing up to 15 mA. The device
features two output enables, each controlling four of the 3-state
outputs.
TYPE
TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)
74F240 4.3 ns 37 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5 V ±10%, T
amb
= 0 °C to +70 °C
PKG DWG #
20-pin plastic DIP N74F240N SOT146-1
20-pin plastic SOL N74F240D SOT163-1
20-pin plastic SSOP II N74F240DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ian, Ibn Data inputs 1.0/1.67 20 µA/1.0 mA
OEa, OEb Output enable inputs (Active-LOW) 1.0/0.33 20 µA/0.2 mA
Yan, Ybn Data outputs 750/106.7 15 mA/64 mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
SF00320
OEa
Ia0
Yb0
Ia1
Yb1
Ia2
Y
b2
Ia3
Y
b3
GND
V
CC
OEb
Y
a0
Ib0
Ya1
Ib1
Y
a2
Ib2
Y
a3
Ib3
LOGIC SYMBOL
V
CC
= Pin 20
GND = Pin 10
SF00321
1
19
OEa
OEb
2 4 6 8 17 15 13 11
181614123579
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
