DS1721
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Capacitive Load for
each Bus Line
C
b
400 pF 8
Input Capacitance C
I
5 pF
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
3. I
DD
specified with T
OUT
pin open.
4. I
DD
specified with V
DD
at 5.0V and SDA,SCL = 5.0V, 0°C to 70°C.
5. After this period, the first clock pulse is generated.
6. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
7. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
R
MAX+t
SU:DAT
1000+250 = 1250 ns before the SCL line is released.
8. C
b
- total capacitance of one bus line in pF.
TIMING DIAGRAMS Figure 7
