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LT3845IFE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LT3845
13
3845fd
at start-up the soft-start circuit will discharge the V
C
pin
voltage below the DC control voltage equivalent to zero
inductor current. This will reduce the input supply inrush
current. The soft-start circuit is disabled once the C
SS
pin
voltage has been charged to 200mV above the internal
reference of 1.231V.
During a V
IN
UVLO, V
CC
UVLO or SHDN UVLO event, the
C
SS
pin voltage is discharged with a 50μA current source.
In normal operation the C
SS
pin voltage is clamped to a
diode above the V
FB
pin voltage. Therefore, the value of the
C
SS
capacitor is relevant to how long of a fault event will
retrigger a soft-start. If any of the above UVLO conditions
occur, the C
SS
pin voltage will be discharged with a 50μA
current source. There is a diode worth of voltage headroom
to ride through the fault before the C
SS
pin voltage enters
its active region and the soft-start function is enabled.
Also, since the C
SS
pin voltage is clamped to a diode above
the V
FB
pin voltage, during a short circuit the C
SS
pin volt-
age is pulled low because the V
FB
pin voltage is low. Once
the short has been removed the V
FB
pin voltage starts to
recover. The soft-start circuit takes control of the output
voltage slew rate once the V
FB
pin voltage has exceeded
the slowly ramping C
SS
pin voltage, reducing the output
voltage overshoot during a short circuit recovery.
Adaptive Nonoverlap (NOL) Output Stage
The FET driver output stages implement adaptive nonover-
lap control. This feature maintains a constant dead time,
preventing shoot-through switch currents, independent
of the type, size or operating conditions of the external
switch elements.
Each of the two switch drivers contains a NOL control
circuit, which monitors the output gate drive signal of the
other switch driver. The NOL control circuits interrupt the
“turn on” command to their associated switch driver until
the other switch gate is fully discharged.
Antislope Compensation
Most current mode switching controllers use slope com-
pensation to prevent current mode instability. The LT3845
is no exception. A slope-compensation circuit imposes an
artifi cial ramp on the sensed current to increase the rising
slope as duty cycle increases. Unfortunately, this additional
APPLICATIONS INFORMATION
ramp corrupts the sensed current value, reducing the
achievable current limit value by the same amount as the
added ramp represents. As such, current limit is typically
reduced as duty cycles increase. The LT3845 contains
circuitry to eliminate the current limit reduction typically
associated with slope compensation. As the slope-com-
pensation ramp is added to the sensed current, a similar
ramp is added to the current limit threshold reference.
The end result is that current limit is not compromised,
so an LT3845 converter can provide full power regardless
of required duty cycle.
Shutdown
The LT3845 SHDN pin uses a bandgap generated reference
threshold of 1.35V. This precision threshold allows use of
the SHDN pin for both logic-level controlled applications
and analog monitoring applications such as power supply
sequencing.
The LT3845 operational status is primarily controlled by
a UVLO circuit on the V
CC
regulator pin. When the IC is
enabled via the SHDN pin, only the V
CC
regulator is enabled.
Switching remains disabled until the UVLO threshold is
achieved at the V
CC
pin, when the remainder of the IC is
enabled and switching commences.
Because an LT3845 controlled converter is a power
transfer device, a voltage that is lower than expected on
the input supply could require currents that exceed the
sourcing capabilities of that supply, causing the system
to lock up in an undervoltage state. Input supply start-up
protection can be achieved by enabling the SHDN pin
using a resistive divider from the V
IN
supply to ground.
Setting the divider output to 1.35V when that supply is at
an adequate voltage prevents an LT3845 converter from
drawing large currents until the input supply is able to
provide the required power. 120mV of input hysteresis
on the SHDN pin allows for almost 10% of input supply
droop before disabling the converter.
R
SENSE
Selection
The current sense resistor, R
SENSE
, monitors the inductor
current of the supply (See Typical Application on front
page). Its value is chosen based on the maximum required
output load current. The LT3845 current sense amplifi er
LT3845
14
3845fd
has a maximum voltage threshold of, typically, 100mV.
Therefore, the peak inductor current is 100mV/R
SENSE
.
The maximum output load current, I
OUT(MAX)
, is the peak
inductor current minus half the peak-to-peak ripple cur-
rent, ΔI
L
.
Allowing adequate margin for ripple current and exter-
nal component tolerances, R
SENSE
can be calculated as
follows:
R
SENSE
=
70mV
I
OUT
(
MAX
)
Typical values for R
SENSE
are in the range of 0.005Ω
to 0.05Ω.
Operating Frequency
The choice of operating frequency is a trade off between
effi ciency and component size. Low frequency operation
improves effi ciency by reducing MOSFET switching losses
and gate charge losses. However, lower frequency opera-
tion requires more inductance for a given amount of ripple
current, resulting in a larger inductor size and higher cost.
If the ripple current is allowed to increase, larger output
capacitors may be required to maintain the same output
ripple. For converters with high step-down V
IN
to V
OUT
ratios, another consideration is the minimum on-time of
the LT3845 (see the Minimum On-time Considerations
section). A fi nal consideration for operating frequency is
that in noise-sensitive communications systems, it is often
desirable to keep the switching noise out of a sensitive
frequency band. The LT3845 uses a constant frequency
APPLICATIONS INFORMATION
architecture that can be programmed over a 100kHz to
500kHz range with a single resistor from the f
SET
pin to
ground, as shown in Figure 2. The nominal voltage on the
f
SET
pin is 1V and the current that fl ows from this pin is
used to charge an internal oscillator capacitor. The value
of R
SET
for a given operating frequency can be chosen
from Figure 2 or from the following equation:
R
SET(kΩ)
= 8.4 • 10
4
• f
SW
(–1.31)
Table 1 lists typical resistor values for common operating
frequencies.
Table 1. Recommended 1% Standard Values
R
SET
(k) f
SW
(kHz)
191 100
118 150
80.6 200
63.4 250
49.9 300
40.2 350
33.2 400
27.4 450
23.2 500
Inductor Selection
The critical parameters for selection of an inductor are
minimum inductance value, volt-second product, satura-
tion current and/or RMS current.
For a given ΔI
L
, The minimum inductance value is calcu-
lated as follows:
L ≥ V
OUT
•
V
IN(MAX)
–V
OUT
f
SW
•V
IN(MAX)
• ΔI
L
f
SW
is the switch frequency.
The typical range of values for ΔI
L
is (0.2 • I
OUT(MAX)
) to
(0.5 • I
OUT(MAX)
), where I
OUT(MAX)
is the maximum load
current of the supply. Using ΔI
L
= 0.3 • I
OUT(MAX)
yields a
good design compromise between inductor performance
versus inductor size and cost. A value of ΔI
L
= 0.3 • I
OUT(MAX)
produces a ±15% of I
OUT(MAX)
ripple current around the DC
output current of the supply. Lower values of ΔI
L
require
larger and more costly magnetics. Higher values of ΔI
L
FREQUENCY (kHz)
0
20
R
SET
(kΩ)
40
80
100
120
400
200
3845 F2
60
200
100
500
300 60
140
160
180
Figure 2. Timing Resistor (R
SET
) Value
LT3845
15
3845fd
APPLICATIONS INFORMATION
will increase the peak currents, requiring more fi ltering
on the input and output of the supply. If ΔI
L
is too high,
the slope compensation circuit is ineffective and current
mode instability may occur at duty cycles greater than
50%. To satisfy slope compensation requirements the
minimum inductance is calculated as follows:
L
MIN
> V
OUT
•
2DC
MAX
–1
DC
MAX
•
R
SENSE
• 8.33
f
SW
The magnetics vendors specify either the saturation cur-
rent, the RMS current or both. When selecting an inductor
based on inductor saturation current, use the peak cur-
rent through the inductor, I
OUT(MAX)
+ ΔI
L
/2. The inductor
saturation current specifi cation is the current at which
the inductance, measured at zero current, decreases by
a specifi ed amount, typically 30%.
When selecting an inductor based on RMS current rating,
use the average current through the inductor, I
OUT(MAX)
.
The RMS current specifi cation is the RMS current at which
the part has a specifi c temperature rise, typically 40°C,
above 25°C ambient.
After calculating the minimum inductance value, the
volt-second product, the saturation current and the RMS
current for your design, select an off-the-shelf inductor.
Contact the Application group at Linear Technology for
further support.
For more detailed information on selecting an inductor,
please see the “Inductor Selection” section of Linear
Technology Application Note 44.
MOSFET Selection
The selection criteria of the external N-channel standard
level power MOSFETs include on resistance (R
DS(ON)
),
reverse transfer capacitance (C
RSS
), maximum drain
source voltage (V
DSS
), total gate charge (Q
G
) and maximum
continuous drain current.
For maximum effi ciency, minimize R
DS(ON)
and C
RSS
.
Low R
DS(ON)
minimizes conduction losses while low C
RSS
minimizes transition losses. The problem is that R
DS(ON)
is inversely related to C
RSS
. In selecting the top MOSFET
balancing the transition losses with the conduction losses
is a good idea while the bottom MOSFET is dominated by
the conduction loss, which is worse during a short-circit
condition or at a very low duty cycle.
Calculate the maximum conduction losses of the
MOSFETs:
P
COND(TOP)
=I
OUT(MAX)
2
•
V
OUT
V
IN
•R
DS(ON)
P
COND(BOT)
=I
OUT(MAX)
2
•
V
IN
–V
OUT
V
IN
•R
DS(ON)
Note that R
DS(ON)
has a large positive temperature depen-
dence. The MOSFET manufacturer’s data sheet contains a
curve, R
DS(ON)
vs Temperature.
In the main MOSFET, transition losses are proportional
to V
IN
2
and can be considerably large in high voltage ap-
plications (V
IN
> 20V). Calculate the maximum transition
losses:
P
TRAN(TOP)
= k • V
IN
2
• I
OUT(MAX)
• C
RSS
• f
SW
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3845 applications.
The total maximum power dissipations of the MOSFET
are:
P
TOP(TOTAL)
= P
COND(MAIN)
+ P
TRAN(MAIN)
P
BOT(TOTAL)
= P
COND(SYNC)
To achieve high supply effi ciency, keep the total power dis-
sipation in each switch to less than 3% of the total output
power. Also, complete a thermal analysis to ensure that
the MOSFET junction temperature is not exceeded.
T
J
= T
A
+ P
(TOTAL)
• θ
JA
where θ
JA
is the package thermal resistance and T
A
is the
ambient temperature. Keep the calculated T
J
below the max-
imum specifi ed junction temperature, typically 150°C.
Note that when V
IN
is high and f
SW
is high, the transition
losses may dominate. A MOSFET with higher R
DS(ON)
and lower C
RSS
may provide higher effi ciency. MOSFETs
with higher voltage V
DSS
specifi cation usually have higher
R
DS(ON)
and lower C
RSS
.
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LT3845IFE#PBF

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Buy LT3845IFE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Voltage Synch Current Mode Step-Down Controller
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