LT3845
19
3845fd
FET carry PGND currents. SGND originates at the negative
terminal of the V
OUT
bypass capacitor, and is the small
signal reference for the LT3845.
Don’t be tempted to run small traces to separate ground
paths. A good ground plane is important as always,
but PGND referred bypass elements must be oriented
such that transient currents in these return paths do not
corrupt the SGND reference.
During the dead-time between switch conduction, the
body diode of the synchronous FET conducts inductor
current. Commutating this diode requires a signifi cant
charge contribution from the main switch. At the instant
the body diode commutates, a current discontinuity is
created and parasitic inductance causes the switch node
to fl y up in response to this discontinuity. High currents
and excessive parasitic inductance can generate ex-
tremely fast dV/dt rise times. This phenomenon can cause
avalanche breakdown in the synchronous FET body di-
ode, signifi cant inductive overshoot on the switch node,
and shoot-through currents via parasitic turn-on of the
synchronous FET. Layout practices and component ori-
entations that minimize parasitic inductance on this node
is critical for reducing these effects.
Ringing waveforms in a converter circuit can lead to device
failure, excessive EMI, or instability. In many cases, you
can damp a ringing waveform with a series RC network
across the offending device. In LT3845 applications, any
ringing will typically occur on the switch node, which
can usually be reduced by placing a snubber across the
synchronous FET. Use of a snubber network, however,
should be considered a last resort. Effective layout practices
typically reduce ringing and overshoot, and will eliminate
the need for such solutions.
Effective grounding techniques are critical for successful
DC/DC converter layouts. Orient power path components
such that current paths in the ground plane do not cross
through signal ground areas. Signal ground refers to
the Exposed Pad on the backside of the LT3845 IC in the
TSSOP package. SGND is referenced to the (–) terminal
of the V
OUT
decoupling capacitor and is used as the con-
verter voltage feedback reference. Power ground currents
are controlled on the LT3845 via the PGND pin, and this
ground references the high current synchronous switch
drive components, as well as the local V
CC
supply. It is
important to keep PGND and SGND voltages consistent
with each other, so separating these grounds with thin
traces is not recommended. When the synchronous
FET is turned on, gate drive surge currents return to the
LT3845 PGND pin from the FET source. The BOOST supply
refresh surge currents also return through this same path.
The synchronous FET must be oriented such that these
PGND return currents do not corrupt the SGND reference.
Problems caused by the PGND return path are generally
recognized during heavy load conditions, and are typically
evidenced as multiple switch pulses occurring during a
single switch cycle. This behavior indicates that SGND is
being corrupted and grounding should be improved. SGND
corruption can often be eliminated, however, by adding a
small capacitor (100pF to 200pF) across the synchronous
switch FET from drain to source.
The high di/dt loop formed by the switch MOSFETs and
the input capacitor (C
IN
) should have short wide traces
to minimize high frequency noise and voltage stress from
inductive ringing. Surface mount components are preferred
to reduce parasitic inductances from component leads.
Connect the drain of the main switch MOSFET directly to
the (+) plate of C
IN
, and connect the source of the syn-
chronous switch MOSFET directly to the (–) terminal of
C
IN
. This capacitor provides the AC current to the switch
MOSFETs. Switch path currents can be controlled by
orienting switch FETs, the switched inductor, and input
and output decoupling capacitors in close proximity to
each other.
Locate the V
CC
and BOOST decoupling capacitors in close
proximity to the IC. These capacitors carry the MOSFET
drivers’ high peak currents. Locate the small-signal
components away from high frequency switching nodes
(BOOST, SW, TG, V
CC
and BG). Small-signal nodes are
oriented on the left side of the LT3845, while high current
switching nodes are oriented on the right side of the IC
to simplify layout. This also helps prevent corruption of
the SGND reference.
Connect the V
FB
pin directly to the feedback resistors
independent of any other nodes, such as the SENSE
–
pin.
The feedback resistors should be connected between
the (+) and (–) terminals of the output capacitor (C
OUT
).
APPLICATIONS INFORMATION
