Data Sheet AD7654
Rev. D | Page 5 of 27
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 23 and Figure 24)
Convert Pulse Width t
1
5 ns
Time Between Conversions
(Normal Mode/Impulse Mode) t
2
2/2.25 µs
CNVST Low to BUSY High Delay
t
3
32 ns
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode) t
4
1.75/2 µs
Aperture Delay t
5
2 ns
End of Conversions to BUSY Low Delay t
6
10 ns
Conversion Time
(Normal Mode/Impulse Mode) t
7
1.75/2 µs
Acquisition Time t
8
250 ns
RESET Pulse Width t
9
10 ns
CNVST Low to EOC High Delay
t
10
30 ns
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode) t
11
1/1.25 µs
EOC Low after Channel A Conversion
t
12
45 ns
EOC High for Channel B Conversion
t
13
0.75 µs
Channel Selection Setup Time t
14
250 ns
Channel Selection Hold Time t
15
30 ns
PARALLEL INTERFACE MODES (See Figure 25 to Figure 29)
CNVST Low to DATA Valid Delay
t
16
1.75/2 µs
DATA Valid to BUSY Low Delay t
17
14 ns
Bus Access Request to DATA Valid t
18
40 ns
Bus Relinquish Time t
19
5 15 ns
A/B Low to Data Valid Delay
t
20
40 ns
MASTER SERIAL INTERFACE MODES (see Figure 30 and Figure 31)
CS Low to SYNC Valid Delay
t
21
10 ns
CS Low to Internal SCLK Valid Delay
1
t
22
10 ns
CS Low to SDOUT Delay
t
23
10 ns
CNVST Low to SYNC Delay (Read During Convert)
(Normal Mode/Impulse Mode) t
24
250/500 ns
SYNC Asserted to SCLK First Edge Delay t
25
3 ns
Internal SCK Period
2
t
26
23 40 ns
Internal SCLK High
2
t
27
12 ns
Internal SCLK Low
2
t
28
7 ns
SDOUT Valid Setup Time
2
t
29
4 ns
SDOUT Valid Hold Time
2
t
30
2 ns
SCLK Last Edge to SYNC Delay
2
t
31
1 ns
CS High to SYNC HI-Z
t
32
10 ns
CS High to Internal SCLK HI-Z
t
33
10 ns
CS High to SDOUT HI-Z
t
34
10 ns
BUSY High in Master Serial Read After Convert
2
t
35
See Table 4
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode) t
36
0.75/1 µs
SYNC Deasserted to BUSY Low Delay t
37
25 ns
