Data Sheet AD7654
Rev. D | Page 15 of 27
AVDD AGND DGND
DVDD
OVDD OGND
SER/PAR
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
REFGND
C
REF
2.5V REF
NOTE 1
REF
REF A
REF B
30
D
CLOCK
AD7654
µC/µP/
DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
A/B
NOTE 7
BYTESWAP
D
V
DD
50k
100nF
1M
INA1
C
C
2.7nF
U1
NOTE 4
NOTE 5
50
+
10
2.7nF
U2
NOTE 4
NOTE 5
50
+
10
INAN
INA2
NOTE 2
NOTE 3
NOTE 6
AD780
10µF
100nF
+
100nF
+
100nF
+
10µF
50
+
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
REF
IS 47µF. SEE VOLTAGE REFERENCE INPUT SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUTS SECTION.
6. OPTIONAL, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
A0
INB1
2.7nF
U3
NOTE 4
NOTE 5
50
+
10
INBN
2.7nF
U4
NOTE 4
NOTE 5
50
+
10
INB2
ANALOG INPUT A1
ANALOG INPUT A2
ANALOG INPUT B1
A
N
A
LOG INPUT B2
C
C
C
C
C
C
10µF
1µF
03057-018
NOTE 1
Figure 19. Typical Connection Diagram (Serial Interface)
AD7654 Data Sheet
Rev. D | Page 16 of 27
TYPICAL CONNECTION DIAGRAM
Figure 19 shows a typical connection diagram for the AD7654.
Different circuitry shown on this diagram is optional and is
discussed in the following sections.
ANALOG INPUTS
Figure 20 shows a simplified analog input section of the AD7654.
INA1
R
A
INB2
C
S
C
S
AGND
A
V
DD
INA2
INAN
INBN
INB1
R
B
03057-019
A0
A0 = L
A0 = L
A0 = H
A0 = H
Figure 20. Simplified Analog Input
The diodes shown in Figure 20 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs. This causes
these diodes to become forward biased and start conducting
current. These diodes can handle a forward-biased current of
120 mA maximum. This condition can eventually occur when
the input buffers (U1) or (U2) supplies are different from
AVDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the device.
This analog input structure allows the sampling of the differential
signal between INx and INxN. Unlike other converters, the INxN
is sampled at the same time as the INx input. By using these
differential inputs, small signals common to both inputs are
rejected.
During the acquisition phase, for ac signals, the AD7654 behaves
like a one-pole RC filter consisting of the equivalent resistance R
A
,
R
B
, and C
S
. The resistors R
A
and R
B
are typically 500 Ω and are a
lumped component made up of some serial resistors and the on
resistance of the switches. The capacitor C
S
is typically 32 pF and is
mainly the ADC sampling capacitor. This one-pole filter with a
typical −3 dB cuto frequency of 10 MHz reduces undesirable
aliasing effects and limits the noise coming from the inputs.
Because the input impedance of the AD7654 is very high, the
AD7654 can be driven directly by a low impedance source
without gain error. To further improve the noise filtering of the
AD7654 analog input circuit, an external one-pole RC filter
between the amplifier output and the ADC input, as shown in
Figure 19, can be used. However, the source impedance has to
be kept low because it affects the ac performance, especially the
total harmonic distortion. The maximum source impedance
depends on the amount of total harmonic distortion (THD) that
can be tolerated. The THD degrades as the source impedance
increases.
INPUT CHANNEL MULTIPLEXER
The AD7654 allows the choice of simultaneously sampling the
inputs pairs INA1/INB1 or INA2/INB2 with the A0 multiplexer
input. When A0 is low, the input pairs INA1/INB1 are selected,
and when A0 is high, the input pairs INA2/INB2 are selected.
Note that INAx is always converted before INBx regardless of
the state of the digital interface channel selection A/
B
pin. Also,
note that the channel selection control A0 should not be changed
during the acquisition phase of the converter. Refer to the
Conversion Control section and Figure 23 for timing details.
DRIVER AMPLIFIER CHOICE
Although the AD7654 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
For multichannel, multiplexed applications, the driver
amplifier and the AD7654 analog input circuit together
must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% or 0.01% is more commonly
specified. It can significantly differ from the settling time at
a 16-bit level and, therefore, it should be verified prior to
the driver selection.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7654. The noise coming from
the driver is filtered by the AD7654 analog input circuit
one-pole low-pass filter made by R
A
, R
B
, and C
S
. The SNR
degradation due to the amplifier is
2
dB3
2
)(
2
56
56
log20
N
LOSS
Nef
SNR
where:
f
–3 dB
is the –3 dB input bandwidth in MHz of the AD7654
(10 MHz) or the cutoff frequency of the input filter, if any is
used.
N is the noise factor of the amplifier (1 if in buffer
configuration).
e
N
is the equivalent input noise voltage of the op amp in
nV/√Hz.
For instance, a driver like the AD8021 with an equivalent
input noise of 2 nV/√Hz, congured as a buer, and thus
with a noise gain of +1, degrades the SNR by only 0.06 dB
with the filter in Figure 19, and by 0.10 dB without.
The driver needs to have a THD performance suitable to
that of the AD7654.
Data Sheet AD7654
Rev. D | Page 17 of 27
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type. The AD8022
can be used where a dual version is needed and a gain of +1 is
used.
The AD829 is another alternative where high frequency
(above 100 kHz) performance is not required. In a gain of +1, it
requires an 82 pF compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.
Refer to Table 8 for some recommended op amps.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1/
ADA4841-2
Very low noise, low distortion, low power,
low frequency
AD829 Very low noise, low frequency
AD8021 Very low noise, high frequency
AD8022 Very low noise, high frequency, dual
AD8655/AD8656
Low noise, 5 V single supply, low power,
low frequency, single/dual
AD8610/AD8620
Low bias current, low frequency,
single/dual
VOLTAGE REFERENCE INPUT
The AD7654 requires an external 2.5 V reference. The reference
input should be applied to REF, REFA, and REFB. The voltage
reference input REF of the AD7654 has a dynamic input
impedance; it should therefore be driven by a low impedance
source with an efficient decoupling. This decoupling depends
on the choice of the voltage reference but usually consists of a
1 μF ceramic capacitor and a low ESR tantalum capacitor
connected to the REFA, REFB, and REFGND inputs with
minimum parasitic inductance. A value of 47 μF is an appropriate
value for the tantalum capacitor when using one of the
recommended reference voltages:
The low noise, low temperature drift AD780, ADR421, and
ADR431 voltage reference.
The low cost AD1582 voltage reference.
For applications using multiple AD7654s with one voltage
reference source, it is recommended that the reference source
drives each ADC in a star configuration with individual
decoupling placed as close as possible to the REF/REFGND
inputs. Also, it is recommended that a buffer, such as the
AD8031/AD8032, be used in this configuration.
Take care with the reference temperature coefficient of the
voltage reference, which directly affects the full-scale accuracy if
this parameter is applicable. For instance, a 15 ppm/°C tempco
of the reference changes the full-scale accuracy by 1 LSB/°C.
POWER SUPPLY
The AD7654 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. To reduce the number of supplies needed, the
digital core (DVDD) can be supplied through a simple RC filter
from the analog supply, as shown in Figure 19. The AD7654
AVDD and DVDD supplies are independent of power supply
sequencing. To ensure the device is free from supply voltage
induced latch-up, OVDD must never exceed DVDD by greater
than 0.3 V. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 21.
FREQUENCY (kHz)
40
PSRR (dB)
100 1000 10000
45
50
55
60
65
70
10
1
03057-020
Figure 21. PSRR vs. Frequency
POWER DISSIPATION
In impulse mode, the AD7654 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 22. This feature makes the AD7654
ideal for very low power battery applications.
Note that the digital interface remains active even during the
acquisition phase. To reduce the operating digital supply
currents even further, the digital inputs need to be driven close
to the power rails (that is, DVDD and DGND), and OVDD
should not exceed DVDD by more than 0.3 V.

AD7654ACPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC ADC 16BIT DUAL 2CH 48LFCSP
Lifecycle:
New from this manufacturer.
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