AD7654 Data Sheet
Rev. D | Page 24 of 27
MICROPROCESSOR INTERFACING
The AD7654 is ideally suited for traditional dc measurement
applications supporting a microprocessor and for ac signal
processing applications interfacing to a digital signal processor.
The AD7654 is designed to interface with either a parallel 8-bit
wide or 16-bit wide interface, a general-purpose serial port, or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7654 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7654 with an SPI equipped DSP, the ADSP-2191M.
SPI INTERFACE (ADSP-2191M)
Figure 35 shows an interface diagram between the AD7654 and
the SPI equipped ADSP-2191M. To accommodate the slower speed
of the DSP, the AD7654 acts as a slave device and data must be
read after conversion. This mode also allows the daisy-chain
feature. The convert command can be initiated in response to
an internal timer interrupt. The 32-bit output data is read with
two serial peripheral interface (SPI) 16-bit wide accesses. The
reading process can be initiated in response to the
end-of-conversion signal (BUSY going low) using an
interrupt line of the DSP. By writing to the SPI control register
(SPICLTx), the serial interface (SPI) on the ADSP-2191M is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt
enable (TIMOD) = 00. To meet all timing requirements, limit
the SPI clock to 17 Mbps, allowing it to read an ADC result in
less than 1 µs. When a higher sampling rate is desired, using one
of the parallel interface modes is recommended.
AD7654*
ADSP-2191M*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
0
3057-034
Figure 35. Interfacing the AD7654 to an SPI Interface
Data Sheet AD7654
Rev. D | Page 25 of 27
APPLICATION HINTS
LAYOUT
The AD7654 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7654 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be separated easily. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7654, or as close as possible to the AD7654.
If the AD7654 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only a star ground point established as close as
possible to the AD7654.
Running digital lines under the device should be avoided
because these couple noise onto the die. The analog ground
plane should be allowed to run under the AD7654 to avoid
noise coupling. Fast switching signals like
CNVST
or clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This reduces the
effect of crosstalk through the board.
The power supply lines to the AD7654 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
AD7654 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply pin—AVDD, DVDD, and
OVDD—close to, and ideally right up against these pins and
their corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.
The DVDD supply of the AD7654 can be a separate supply or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see Figure 19) and the system supply to OVDD and
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.
The AD7654 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the
analog input signal. REFGND senses the reference voltage and,
because it carries pulsed currents, should be a low impedance
return to the reference. AGND is the ground to which most
internal ADC analog signals are referenced; it must be connected
with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane, depending
on the configuration. OGND is connected to the digital system
ground.
AD7654 Data Sheet
Rev. D | Page 26 of 27
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
3.5°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 36. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
112408-B
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
P
I
N
1
I
N
D
I
C
A
T
O
R
5.20
5.10 SQ
5.00
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.25 MIN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
Figure 37. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters

AD7654ACPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC ADC 16BIT DUAL 2CH 48LFCSP
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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