DSDK2000 Datasheet DSDK2000 | P10-P12

DK2000 High-Performance Demo Kit Motherboard

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Table 2. Register Subfield Definitions

SUBFIELD DESCRIPTION

address

rname

rtype

0 = invalid – not displayed, read, written, or initialized

1 = read-only – cannot be written

2 = read/write – can be read and written

3 = status1 – read operation is preceded by a write of 0xFF

5 = error – cannot be written

6 = test – can be read and written

7 = status2 – read operation is are followed by a write of the value read

bus

This field should be always be “1” for definition files used with DK2000.

ivalue

Initial value written to the register during initialization if the SETUP field is “on.” Two-digit hexadecimal

format of the form “00.”

position

field. These numbers are for the user only; this field is not read by the software. For proper use with the

DISPLAY field, register definitions should be numbered consecutively starting from 0 with no missing or

repeated numbers.

fullname

Full register name. A string of £ 50 characters that is displayed at the top of the bitmap display when the

b7, b6, b5, b4,

b3, b2, b1, b0

Bit names. Each is a string of £ 6 characters that is displayed in the bit map display.

Creating and Editing Initialization (.INI) Files

initialize the register set from an initialization file, choose File®Register .INI File®Load .INI File. To save the state

of a register set to an initialization file, choose File®Register .INI File®Build .INI File. Only the registers of the

currently visible definition file are affected by these commands.

Terminal Mode

In addition to Register View mode and Demo mode, the ChipView software also offers Terminal mode, which gives

direct access to the processor. The commands that can be entered from Terminal mode are listed in Table 3

. The

interface specifications are 38,400 baud, 8 data bits, 1 stop bit, no parity, no flow control, ANSI emulation. Locally

typed characters are echoed by the DK2000, not the terminal software.

Table 3. Terminal Mode Commands

COMMAND FUNCTION

F Display firmware version.

Help | ? Display help text.

RB <address>

Read from byte at absolute address, no offset added to address.

Example: RB 90000000 reads first address in CS9.

RW <address> Read 16-bit word at absolute address, no offset added to address.

RL <address> Read 32-bit long word at absolute address, no offset added to address.

Repeat <count> <command string>

Repeats the command given by <command string> the number of times

specified by the <count> argument.

setDev <0–F> Set default device number for use with the X command.

setSlot <0–3> Set default slot number for use with the X command.

TimInfo [slot number]

Displays information about the attached daughter cards. If no slot number is

given, TimInfo displays concise information about all four slots.

WB <address> <value>

Write byte to absolute address, no offset added to address.

Example: WB 90000000 FF writes 0xFF to the first address in CS9.

WW <address> <value> Write 16-bit word to absolute address, no offset added to address.

WL <address> <value> Write 32-bit long word to absolute address, no offset added to address.

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Table 3. Terminal Mode Commands (continued)

COMMAND FUNCTION

X <addr> [, <endaddr>] [= <value>]

Read or write to daughter card slot addresses. The fifth hex digit of the address

is the daughter card slot number. The fourth hex digit of the address is the

device number. Addresses with fewer than four hex digits are added to the

addresses of the default slot, as set by the setSlot command, plus the default

device, as set by the setDev command.

Examples:

$ X 31020 = FF {write FFh to slot 3, device 1, address 020h}

$ X 31999 {read slot 3, device 1, address 999h}

FF {value stored in slot 3, device 1, address 999h}

$ X 55 {read address 55h of default slot/device as set by setSlot

and setDev}

32 {value stored in default slot/device, address 55h}

$ X 20, 30 = 5 {write 05h to default slot/device, addresses 20 to 30h}

The following commands are used by Demo mode. They are not recommended for use in Terminal mode.

CTRL <…> <slot>

The DK2000 firmware includes T1/E1 device driver code written by NComm.

CTRL calls the TE1DCTRL device driver API with the indicated parameters (see

T1/E1 driver code documentation for details). The slot number on the end is not

passed through to the API but is simply used to determine which device driver to

call.

Example: CTRL 0 400 0 {resets span 0 of slot 0}

POLL <…> <slot>

The DK2000 firmware includes T1/E1 device driver code written by NComm.

POLL calls the TE1DPOLL device driver API with the indicated parameters (see

T1/E1 driver code documentation for details). The slot number on the end is not

passed through to the API but is simply used to determine which device driver to

call.

Example: POLL 0 600 0 {polls for RLOS on span 0 of slot 0}

Additional Development Resources

The following resources are available for continued development using the DK2000:

NComm, Inc.

T1/E1 Trunk Management Software (TMS

™

)

www.ncomm.com

Wind River International

The DK2000 firmware uses the VxWorks real-time operating system (RTOS) from Wind River.

www.windriver.com

Electro Surface Technologies, Inc. (EST) (A division of Wind River)

The DK2000 is compatible with the VisionClick C/C++ source-level debugger/flash programming tool.

www.est.com

TMS is a trademark of NComm Inc.

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APPENDIX

MPC8260 CPU and Memory Map

CPU Core. The DK2000 development platform is based on the Motorola MPC8260 PowerQUICC II processor. This

processor integrates a PowerPC core, a system interface unit (SIU), and a communications processor module

(CPM).

The DK2000 board is configured with a 66MHz oscillator providing the system bus clock and SIU clocks. The

MPC8260 internally multiplies the system clock to 133MHz for the CPM and to 200MHz for the PowerPC processor

core. The internal clock multiplier is determined during PORESET (power-on RESET) based on the states of

RSTCONF, MODCLK [1–3], and the values in the hard-reset configuration word bits 28–31. The DK2000 board

wires RSTCONF low, forcing the MPC8260 to read the hard-reset configuration word from the beginning of flash

memory. DK2000 ’s default configuration word is configurable depending on your application. Refer to the Motorola

MPC8260 PowerQUICC II User’s Manual, Section 5.4.1 (www.motorola.com

) for detailed information about reset

configuration.

RESET CONFIGURATION BYTE DEFAULT DK2000 VALUE

0 0x1E

1 0x82

2 0x83

3 0x45

SDRAM. The DK2000 development platform contains 64MB of SDRAM controlled by the MPC8260’s internal

SDRAM controller. The SDRAM is connected to the MPC8260’s chip select 2 (CS2).

Level 2 Cache Control. To provide additional performance, the DK2000 board has been designed with the option

for 256kB, 512kB, or 1MB of L2 cache. One, two, or four MPC2605s are used as the L2 cache. The MPC2605 can

function in either copy-back mode or write-through mode. The L2 cache can be enabled and disabled though a

L2_TAG_CLR_L, AND L2_UPDATE_INH_L. The board powers up with the L2 cache disabled; software must

configure the MPC8260 to work with the L2 cache before enabling it. See Table 7

for a description of the L2 cache

control register.

FLASH—2 Banks. The DK2000 development platform has 4MB of flash memory organized into two banks. Each

bank is organized as 512kB x 32, consisting of four Atmel AT49LV040 devices that are socketed for easy removal

and external programming. Through jumper selection, either of the two flash banks can be configured as the boot

ROM. The flash banks are controlled by the MPC8260’s chip selects 0 and 1 (CS0 and CS1). The chip-select

assignment for each bank is a jumper-configurable selection. The silk screening on the board next to the BOOT

CONFIG header (P7) indicates which byte lane each FLASH device is attached to. See Figure 4

EEPROM. A 16kb EEPROM is connected to the SPIÔ port on the MPC8260. The EEPROM is organized as 2048

x 8.

Chip-Select Mapping

The MPC8260 has 12 chip-select outputs. The DK2000 board uses these chip selects as defined in Table 4.

CS0 and CS1. Chip selects 0 and 1 are connected to the two 2MB flash banks through jumper block P7. To

connect CS0 to bank 0 and CS1 to bank 1, place a jumper across pins 1 and 2 and another jumper across pins 3

and 4. To connect CS0 to bank 1 and CS1 to bank 0, place a jumper across pins 1 and 3 and another jumper

across pins 2 and 4. See Figure 5

CS7. Chip select 7 addresses the STIM board ID and LED control register as shown in Table 5

SPI is a trademark of Motorola, Inc.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

DSDK2000

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Networking Development Tools High Performance Demo Kit Platform

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