DK2000 High-Performance Demo Kit Motherboard
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Table 4. Chip Selects and Memory Map
CHIP SELECT FUNCTION/DEVICE STARTING ADDRESS
CS0 Flash Bank 0 (Boot ROM) 0x10000000
CS1 Flash Bank 1 0x20000000
CS2 SDRAM 0x00000000
CS3 Daughter Card Slot 0 0x30000000
CS4 Daughter Card Slot 1 0x40000000
CS5 Daughter Card Slot 2 0x50000000
CS6 Daughter Card Slot 3 0x60000000
CS7 STIM ID Control 0x70000000
CS8 STIM Device Control 0x80000000
CS9 Peripherals 0x90000000
CS10 Unused (pin assigned to different function)
CS11 EPLD 0xB0000000
Note 1: CS0 and CS1 can be swapped with jumper settings.
Note 2: The Dallas Semiconductor device is typically located at the daughter card address + 0x1000. Example: For a daughter card in slot 2,
the device address begins at 0x50001000 (0x50000000 plus the daughter card offset of 0x1000).
Table 5. Chip Select 7 Mapping
ADDRESS OFFSET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
0x00 STIM ID
0x02 STIM LED N/A N/A N/A N/A N/A N/A
The STIM ID register contains the ID of the STIM board. Value is 0xFF if no STIM card is present.
The STIM LED register controls the LED on the STIM as follows:
00 LED is OFF
01 LED is ON and is RED
10 LED is ON and is GREEN
11 LED is OFF
Figure 5. Flash Bank Configurations
CS9. Chip select 9 is connected to the EPLD and is used to address several devices. The EPLD decodes CS9
accesses according to the Table 6
.
Table 6. Chip Select 9 Mapping
ADDRESS OFFSET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
0x0000 Slot 1 Daughter Card ID Slot 0 Daughter Card ID
0x1000 Slot 3 Daughter Card ID Slot 4 Daughter Card ID
0x2000 Slot 3 LED Slot 2 LED Slot 1 LED Slot 0 LED
0x3000 FPGA
The Slot Daughter Card ID registers are used to determine the types of daughter cards present in the system.
Typical software implementation reads the daughter card ID values and assigns device drivers based on the
values. Daughter card IDs that are the value 0xE indicate an extended daughter card ID. The extended daughter
card ID can be read at offset 0 of the slot address. A value of 0xF indicates that a daughter card is not present in
the slot.
13 3 , 1
14 4 , 2
P7
13 3 , 1
14 4 , 2
CS0 TO BANK 0, CS1 TO BANK 1
CS0 TO BANK 1, CS1 TO BANK 0
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The Slot LED registers control the LEDs on the daughter cards as follows:
00 LED is OFF
01 LED is ON and is RED
10 LED is ON and is GREEN
11 LED is OFF
The FPGA register holds the address of the FPGA on the board. This is reserved for future use. The FPGA is
unpopulated on most boards.
CS11. Chip select 11 is used by the EPLD. The current EPLD implementation has the registers defined in Table 7
.
Table 7. Chip Select 11 Mapping
ADDRESS OFFSET BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
0x00 EPLD Version Number
0x01 UPDATE TAG_CLR FLUSH MISS_INH Unused
UPDATE: Reset to 0. When 0, inhibits updating of the L2 cache.
TAG_CLR: Reset to 0. When 0, clears the L2 cache Tag.
FLUSH: Reset to 0. When 0, flushes the L2 cache.
MISS_INH: Reset to 0. When 0, forces all L2 cache accesses to miss.
MPC8260 I/O Pin Mapping
The MPC8260 has 120 I/O pins that can be configured for special-purpose or general-purpose I/O. The DK2000
development platform takes advantage of as much of the I/O capability as possible. Table 8
shows how the I/O
pins are connected on the DK2000 board. Table 9
and Table 10 add details on some of the special-purpose pin
assignments.
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Table 8. MPC8260 I/O Pin Assignments
PORT A PORT B PORT C PORT D
PIN CONNECTOR PIN CONNECTOR PIN CONNECTOR PIN CONNECTOR
0 N.C. 0 0 Ethernet 0
1 N.C. 1 1 STIM 1
2 STIM 2 2 STIM 2
3 STIM 3
N/A
3 STIM 3
N/A
4 N.C. 4 Ethernet 4 Ethernet 4 Daughter Card 3
5 N.C. 5 Ethernet 5 Ethernet 5 N.C.
6 Daughter Card 0 6 Ethernet 6 Daughter Card 0–3 6 N.C.
7 Daughter Card 0 7 Ethernet 7 Daughter Card 0–3 7 Daughter Card 0–3
8 Daughter Card 0 8 Ethernet 8 Ethernet 8 RS-232
9 Daughter Card 0 9 Ethernet 9
Daughter Card 0–3,
Daughter Card
9 RS-232
10
Daughter Card
0–3
10 Ethernet 10 Ethernet 10 Daughter Card 1
11
Daughter Card
0–3
11 Ethernet 11 Ethernet 11 Daughter Card 1
12
Daughter Card
0–3
12 Ethernet 12 Daughter Card 0–3 12 Daughter Card 1
13
Daughter Card
0–3
13 Ethernet 13 Daughter Card 0–3 13 Daughter Card 1
14
Daughter Card
0–3
14 Ethernet 14 Daughter Card 0–3 14
I
2
CÔ
15
Daughter Card
0–3
15 Ethernet 15 Daughter Card 0–3 15
I
2
C
16
Daughter Card
0–3
16 Ethernet 16 Ethernet 16 Daughter Card 2
17
Daughter Card
0–3
17 Ethernet 17 Ethernet 17 Daughter Card 0–3
18
Daughter Card
0–3
18 Ethernet 18
Daughter Card 0–3,
STIM
18 Daughter Card 0–3
19
Daughter Card
0–3
19 Ethernet 19
Daughter Card 0–3,
STIM
19 Daughter Card 0–3
20
Daughter Card
0–3
20 STIM 20 Daughter Card 0–3 20
Daughter Card 0–3,
STIM
21
Daughter Card
0–3
21 STIM 21 Daughter Card 0–3 21
Daughter Card 0–3,
STIM
22
Daughter Card
0–3
22 STIM 22 Daughter Card 1 22
Daughter Card 0–3,
STIM
23
Daughter Card
0–3
23 STIM 23 Daughter Card 1 23 Daughter Card 3
24
Daughter Card
0–3
24 STIM 24 Daughter Card 3 24 Daughter Card 3
25
Daughter Card
0–3
25 STIM 25 Daughter Card 3 25 Daughter Card 3
26
Daughter Card
0–3
26 STIM 26 Daughter Card 2 26 Daughter Card 2
27
Daughter Card
0–3
27 STIM 27 Daughter Card 2 27 Daughter Card 2
28
Daughter Card
0–3
28 Byte Blaster 28 STIM 28 Daughter Card 2
29
Daughter Card
0–3
29 Byte Blaster 29 STIM 29 Daughter Card 0–3
30
Daughter Card
0–3
30 Byte Blaster 30 Daughter Card 1 30 N.C.
31
Daughter Card
0–3
31 Byte Blaster 31 Daughter Card 1 31 N.C.
I
2
C
a
li
d
b.

DSDK2000

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Networking Development Tools High Performance Demo Kit Platform
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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