COMMERCIAL TEMPERATURE RANGE
20
IDTCV133
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
DIFFERENTIAL CLOCK TRISTATE
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PD and CPU_STOP#
mode and the SRC clock is configurable to be driven or tristated during PCI_STOP# and PD mode. Each differential clock (SRC, CPU[2:0]) output can be
disabled by setting the corresponding output’s register OE bit to “0” (disable). Disabled outputs are to be tristated regardless of “CPU_STOP”, “SRC_STOP”
and “PD” register bit settings.
Signal Pin PD Pin CPU_STOP# CPU_STOPTristate Bit PD Tristate Bit Non-Stoppable Outputs Stoppable Outputs
CPU 0 1 X X Running Running
CPU 0 0 0 X Running Driven at IREF x 6
CPU 0 0 1 X Running Tristate
CPU 1 X X 0 Driven at IREF x 2 Driven at IREF x 2
CP U 1 X X 1 Tristate Tristate
NOTES:
1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
Signal Pin PD Pin PCI_STOP# PCI_STOPTristate Bit PD Tristate Bit Non-Stoppable Outputs Stoppable Outputs
SRC 0 1 X X Running Running
SRC 0 0 0 X Running Driven at IREF x 6
SRC 0 0 1 X Running Tristate
SRC 1 X X 0 Driven at IREF x 2 Driven at IREF x 2
SRC 1 X X 1 Tristate Tristate
NOTES:
1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
Signal Pin PD PD Tristate Bit Output
DOT96 1 X Running
DOT96 0 0 Driven at IREF x 2
DOT96 0 1 Tristate
NOTES:
1. DOT output has two corresponding control register bits; OE and PD.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
TRISTATE DOT96 CLOCK CONTROL
