COMMERCIAL TEMPERATURE RANGE
IDTCV133
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
7
BYTE 3
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 LVDS RW 0
1 SRC1 RW 0
2 SRC2 Allow controlled by Free running, not Stopped with RW 0
3 SRC3 PCI_STOP# assertion affected by PCI_STOP# PCI_STOP# RW 0
4 SRC4 RW 0
5 SRC5 RW 0
6 Reserved RW 0
7 SRC7 Allow controlled by Free running, not Stopped with RW 0
PCI_STOP# assertion affected by PCI_STOP# PCI_STOP#
BYTE 4
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# Allow control of CPU0 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
1 CPU1, CPU1# Allow control of CPU1 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
2 CPU2, CPU2# Allow control of CPU2 Not stopped Stopped with RW 1
with assertion of CPU_STOP# by CPU_STOP# CPU_STOP#
3 PCIF0 Allow controlled by Not stopped Stopped with RW 0
4 PCIF1 PCI_STOP# assertion by PCI_STOP# PCI_STOP# RW 0
5 Reserved RW 0
6 DOT96 DOT96 power down drive mode Driven in power down Tristate RW 0
7 Reserved RW 0
BYTE 5
Bit Output(s) Affected Description / Function 0 1 Type Power On
0 CPU0, CPU0# CPU0 PD drive mode Driven in power down Tristate in power down RW 0
1 CPU1, CPU1# CPU1 PD drive mode Driven in power down Tristate in power down RW 0
2 CPU2, CPU2# CPU2 PD drive mode Driven in power down Tristate in power down RW 0
3 SRCS SRC PD drive mode Driven in power down Tristate in power down RW 0
4 CPU0 CPU0 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
5 CPU1 CPU1 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
6 CPU2 CPU2 CPU_STOP drive mode Driven in CPU_STOP# Tristate when stopped RW 0
7 SRCS SRC PCI_STOP drive mode Driven in PCI_STOP Tristate when stopped RW 0