ADCLK950BCPZ Datasheet ADCLK950BCPZ, ADCLK950BCPZ-REEL7 | P7-P9

ADCLK950 Data Sheet

Rev. B | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN_SEL

CLK0

V

REF

0

V

T

0

CLK1

V

T

1

V

REF

1

V

EE

V

CC

Q9

Q8

Q7

Q6

V

CC

Q8

Q3

Q2

Q1

Q0

V

CC

Q3

V

CC

NC

Q5

Q4

NC

V

CC

NC

V

CC

08279-002

1

2

3

4

5

6

7

8

9

10

23

24

25

26

27

28

29

30

22

21

11

12

13

15

17

16

18

19

20

14

33

34

35

36

37

38

39

40

32

31

ADCLK950

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EPAD MUST BE SOLDERED TO THE V

EE

POWER PLANE.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 IN_SEL Input Select. Logic 0 selects CLK0 and

CLK0

inputs. Logic 1 selects CLK1 and

CLK1

inputs.

2 CLK0 Differential Input (Positive) 0.

3

CLK0

Differential Input (Negative) 0.

4 V

REF

0 Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and

CLK0

inputs.

5 V

T

0 Center Tap. Center tap of a 100 Ω input resistor for CLK0 and

CLK0

inputs.

6 CLK1 Differential Input (Positive) 1.

7

CLK1

Differential Input (Negative) 1.

8 V

T

1 Center Tap. Center tap of a 100 Ω input resistor for CLK1 and

CLK1

inputs.

9 V

REF

1 Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and

CLK1

inputs.

10 V

EE

Negative Supply Pin.

11, 20, 21,

30, 31, 40

V

CC

Positive Supply Pin.

12, 13

Q9

, Q9 Differential LVPECL Outputs.

14, 15

Q8

, Q8 Differential LVPECL Outputs.

16, 17

Q7

, Q7 Differential LVPECL Outputs.

18, 19

Q6

, Q6 Differential LVPECL Outputs.

22, 23, 28,

29

NC No Connection

24, 25

Q5

, Q5 Differential LVPECL Outputs.

26, 27

Q4

, Q4 Differential LVPECL Outputs.

32, 33

Q3

, Q3

Differential LVPECL Outputs.

34, 35

Q2

, Q2 Differential LVPECL Outputs.

36, 37

Q1

, Q1 Differential LVPECL Outputs.

38, 39

Q0

, Q0 Differential LVPECL Outputs.

EPAD Exposed Pad. The EPAD must be soldered to the V

EE

power plane.

Data Sheet ADCLK950

Rev. B | Page 7 of 12

TYPICAL PERFORMANCE CHARACTERISTICS

V

CC

= 3.3 V, V

EE

= 0 V, V

ICM

= V

REF

x, T

A

= 25°C, clock outputs terminated at 50 Ω to V

CC

− 2 V, unless otherwise noted.

C3

C4

C3

100mV/DIV 500ps/DIV

08279-003

Figure 3. LVPECL Output Waveform @ 200 MHz

1.8

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

0 1000 2000 3000 4000 5000

DIFFERENTIAL OUTPUT VOLTAGE (V)

FREQUENCY (MHz)

08279-004

Figure 4. Differential Output Voltage vs. Frequency, V

ID

> 1.1 V p-p

225

180

185

190

195

200

205

210

215

220

01.81.61.41.21.00.80.60.40.2

PROPAGATION DELAY (ps)

DIFFERENTIAL INPUT VOLTAGE SWING (V)

08279-005

Figure 5. Propagation Delay vs. Differential Input Voltage

C4

C3

C4

100mV/DIV 100ps/DIV

08279-006

Figure 6. LVPECL Output Waveform @ 1000 MHz

214

213

212

211

210

209

208

207

–40 806040200–20

PROPAGATION DELAY (ps)

TEMPERATURE (°C)

08279-007

Figure 7. Propagation Delay vs. Temperature, V

ID

= 1.6 V p-p

230

190

200

210

220

0.9 3.12.92.72.52.32.11.91.71.51.31.1

PROPAGATION DELAY (ps)

DC COMMON-MODE VOLTAGE (V)

+85°C

+25°C

–40°C

08279-008

Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs.

Temperature, Input Slew Rate > 25 V/ns

ADCLK950 Data Sheet

Rev. B | Page 8 of 12

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

2.75 2.85 2.95 3.05

3.15

3.25 3.35

3.45 3.55

3.65

3.75

DIFFERENTIAL OUTPUT VOLTAGE SWING (V)

POWER SUPPLY (V)

+85°C

+25°C

–40°C

08279-009

Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs.

Temperature, V

ID

= 1.6 V p-p

400

350

300

250

200

150

100

50

2.75 3.753.503.253.00

SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

ICC

IEE

+85°C

+25°C

–40°C

08279-010

Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature,

All Outputs Loaded (50 Ω to V

CC

− 2 V)

–90

–170

–160

–150

–140

–130

–120

–110

–100

10

100

1k

10k

100k

1M 10M 100M

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET (Hz)

CLOCK SOURCE

ADCLK950

ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT

E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A

WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),

WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A

WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).

08279-011

Figure 11. Absolute Phase Noise Measured @1 GHz

300

250

200

150

100

50

0

0 252015105

RANDOM JITTER (f

S

rms)

INPUT SLEW RATE (V/ns)

08279-012

Figure 12. RMS Random Jitter vs. Input Slew Rate, V

ID

Method

ADCLK950BCPZ

ADCLK950BCPZ

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