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CAV24C64WE-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
© Semiconductor Components Industries, LLC, 2017
April, 2018 − Rev. 4
1 Publication Order Number:
CAV24C64/D
CAV24C64
EEPROM Serial 64-Kb I
2
C
- Auto Grade
Description
The CAV24C64 is a EEPROM Serial 64−Kb I
2
C − Auto Grade
device, internally organized as 8192 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz) and Fast (400 kHz) I
2
C protocol.
External address pins make it possible to address up to eight
CAV24C64 devices on the same bus.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• Supports Standard and Fast I
2
C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• SOIC, TSSOP 8−lead, and WLCSP 4−Ball Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
Figure 1. Functional Symbol
SDA
SCL
WP
CAV24C64
V
CC
V
SS
A
2
, A
1
, A
0
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
SOIC−8
W SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
Device Address InputA
0
, A
1
, A
2
Serial Data Input/OutputSDA
Serial Clock InputSCL
Write Protect InputWP
Power SupplyV
CC
GroundV
SS
FunctionPin Name
PIN FUNCTION
WLCSP−4
C4C SUFFIX
CASE 567JY
PIN CONFIGURATIONS (Top Views)
SOIC (W), TSSOP (Y)
SDA
WP
V
CC
V
SS
A
2
A
1
A
0
1
SCL
WLCSP (C4C)
A1 A2
B1 B2
SDA
V
SS
SCL
V
CC
1
SOIC−8 WIDE
X SUFFIX
CASE 751BE
CAV24C64
www.onsemi.com
2
DEVICE MARKINGS
(SOIC−8)(TSSOP−8)
C64F
AYMXXX
C64F = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G = Pb−Free Package
24C64F = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1-9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G = Pb−Free Package
24C64F
AYMXXX
G
G
For the location of Pin 1,
please consult the corre-
sponding package drawing.
A = Specific Device Code
YW = Production Date Code
A
YW
(WLCSP−4)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A
0
, A
1
, A
2
and WP should not exceed V
CC
+ 1 V for more than 20 ns, while voltage on the I
2
C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
N
END
(Note 3) Endurance 1,000,000 Program/Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CCR
Read Current Read, f
SCL
= 400 kHz 1 mA
I
CCW
Write Current Write, f
SCL
= 400 kHz 2 mA
I
SB
Standby Current All I/O Pins at GND or V
CC
T
A
= −40°C to +125°C 5
mA
I
L
I/O Pin Leakage Pin at GND or V
CC
2
mA
V
IL
Input Low Voltage −0.5 0.3 x V
CC
V
V
IH
Input High Voltage
A
0
, A
1
, A
2
and WP 0.7 x V
CC
V
CC
+ 0.5
V
SCL and SDA 0.7 x V
CC
5.5
V
OL
Output Low Voltage V
CC
> 2.5 V, I
OL
= 3 mA 0.4 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
CAV24C64
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3
Table 4. PIN IMPEDANCE CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter Conditions Max Units
C
IN
(Note 4) SDA I/O Pin Capacitance V
IN
= 0 V, T
A
= 25°C 8 pF
C
IN
(Note 4) Input Capacitance (other pins) V
IN
= 0 V, T
A
= 25°C 6 pF
I
WP
(Note 5) WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V 130 mA
V
IN
< V
IH
, V
CC
= 3.3 V 120
V
IN
< V
IH
, V
CC
= 2.5 V 80
V
IN
> V
IH
2
I
A
(Note 5) Address Input Current
(A0, A1, A2)
Product Rev F
V
IN
< V
IH
, V
CC
= 5.5 V 50 mA
V
IN
< V
IH
, V
CC
= 3.3 V 35
V
IN
< V
IH
, V
CC
= 2.5 V 25
V
IN
> V
IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS (V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.) (Note 6)
Symbol
Parameter
Standard Fast
Units
Min Max Min Max
F
SCL
Clock Frequency 100 400 kHz
t
HD:STA
START Condition Hold Time 4 0.6
ms
t
LOW
Low Period of SCL Clock 4.7 1.3
ms
t
HIGH
High Period of SCL Clock 4 0.6
ms
t
SU:STA
START Condition Setup Time 4.7 0.6
ms
t
HD:DAT
Data In Hold Time 0 0
ms
t
SU:DAT
Data In Setup Time 250 100 ns
t
R
SDA and SCL Rise Time 1000 300 ns
t
F
(Note 6) SDA and SCL Fall Time 300 300 ns
t
SU:STO
STOP Condition Setup Time 4 0.6
ms
t
BUF
Bus Free Time Between STOP and START 4.7 1.3
ms
t
AA
SCL Low to Data Out Valid 3.5 0.9
ms
t
DH
Data Out Hold Time 100 100 ns
T
i
(Note 6) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
t
SU:WP
WP Setup Time 0 0
ms
t
HD:WP
WP Hold Time 2.5 2.5
ms
t
WR
Write Cycle Time 5 5 ms
t
PU
(Notes 7, 8) Power−up to Ready Mode 1 1 ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 x V
CC
to 0.8 x V
CC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x V
CC
, 0.7 x V
CC
Output Reference Levels 0.5 x V
CC
Output Load Current Source: I
OL
= 3 mA; C
L
= 100 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CAV24C64WE-GT3

Mfr. #:
Buy CAV24C64WE-GT3
Manufacturer:
ON Semiconductor
Description:
EEPROM 64KB I2C SER EEPROM
Lifecycle:
New from this manufacturer.
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