ISL76322ARZ Datasheet ISL76322ARZ, ISL76322ARZ-TK, ISL76322ARZ-T7A | P10-P12

ISL76322

May 6, 2015

FN7611.3

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Applications

Detailed Description and Operation

A pair of ISL76322 SERDES transports 16-bit parallel video for

the ISL76322 along with auxiliary data over a single 100Ω

differential cable either to a display or from a camera. Auxiliary

data is transferred in both directions every video frame. This

feature can be used for remote configuration and telemetry.

The benefits include lower EMI, lower costs, greater reliability and

space savings. The same device can be configured to be either a

serializer or deserializer by setting one pin (VIDEO_TX), simplifying

inventory. RGBA/C, VSYNC, HSYNC, and DATAEN pins are inputs in

serializer mode and outputs in deserializer mode.

The video data presented to the serializer on the parallel LVCMOS

bus is serialized into a high-speed differential signal. This

differential signal is converted back to parallel video at the

remote end by the deserializer. The Side Channel data (auxiliary

data) is transferred between the SERDES pair during the first two

lines of the vertical video blanking interval.

When the side-channel is enabled, which is the default, there will

be a number of PCLK cycles uncertainty from frame-to-frame.

This should not cause sync problems with most displays as this

occurs during the vertical front porch of the blanking period.

When properly configured, the SERDES link supports end-to-end

transport with fewer than one error in 10

bits.

Differential Signals and Termination

The ISL76322 serializes the 16-bit parallel data plus 3 sync

signals at 20x the PCLK_IN frequency. The extra 2 bits per word

come from the 8b/10b encoding scheme which helps create the

highest quality serial link.

The high bit rate of the differential serial data requires special

care in the layout of traces on PCBs, in the choice and assembly

of connectors, and in the cables themselves.

PCB traces need to be adjacent, matched in length and drawn to

result in a differential 100Ω controlled impedance. For best EMI

performance, the cable should be low loss and have a differential

100Ω impedance. The maximum cable length for a functioning

link is dependent on the PCLK_IN frequency, the cable loss and

impedance, as well as the pre-emphasis and equalization

settings. Functioning links of 25 meters are often possible at the

maximum frequency.

SERIOP and SERION pins incorporate internal differential

termination of the serial signal lines.

SERIO Pin AC-Coupling

AC-coupling minimizes the effects of DC common mode voltage

difference and local power supply variations between two

SERDES. The serializer outputs DC balanced 8b/10b line code,

which allows AC-coupling.

The AC-coupling capacitor on SERIO pins must be 27nF on the

serializer board and 27nF on the deserializer board. The value of the

AC-coupling capacitor is very critical since a value too small will

attenuate the high-speed signal at low clock rate. A value too big will

slow down the turn around time for the side-channel. It is an

advantage to have the pair of capacitors as closely matched as

possible.

Receiver Reference Clock (REF_CLK)

The reference clock (REF_CLK) for the PLL is fed into PCLK_IN

pin. REF_CLK is used to recover the clock from the high-speed

serial stream. REF_CLK is very sensitive to any instability. The

following conditions must be met at all times after power is

applied to the deserializer, or else the deserializer may need a

manual reset:

• VDD must be applied and stable

• REF_CLK frequency must be within the limits specified

• REF_CLK amplitude must be stable

A simple 3.3V CMOS crystal oscillator can be used for REF_CLK

Power Supply Sequencing

The 3.3V supply must be higher than the 1.8V supply at all times,

including during power-up and power-down. To meet this

requirement, the 3.3V supply must be powered up before the

1.8V supply.

For the deserializer, REF_CLK must not be applied before the

device is fully powered up. Applying REF_CLK before power-up

FIGURE 4. PARALLEL VIDEO OUTPUT TIMING

DESERIALIZER MODE

PCLK_OUT

(RISING EDGE

DEFAULT)

1/FOUT

ODC

VALID DATA VALID DATA VALID DATAPREVIOUS DATA HELD

RGBA[7:0],

RGBC[7:0]

HSYNC OR VSYNC

( HVSYNCPOL = ‘0’)

DATAEN

(ACTIVE ‘1’ DEFAULT)

ISL76322

May 6, 2015

FN7611.3

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may require the deserializer to be manually reset. A 10ms delay

after the 1.8V supply is powered up guarantees normal

operation.

Power Supply Bypassing and Layout

The serializer and deserializer functions rely on the stable

functioning of PLLs locked to local reference sources or locked to

an incoming signal. It is important that the various supplies

(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a

wide range of frequencies, from below the typical loop bandwidth

of the PLL to approaching the signal bit rate of the serial data. A

combination of different values of capacitors from 1000pF to

5µF or more with low ESR characteristics is generally required.

The parallel LVCMOS VDD_IO

supply is inherently less sensitive,

but since the RGB and SYNC/DATAEN signals can all swing on the

same clock edge, the current in these pins, and the

corresponding GND pins, can undergo substantial current flow

changes. Once again, a combination of different values of

capacitors over a wide range, with low ESR characteristics, is

desirable.

A set of arrangements of this type is shown in Figure 5

, where

each supply is bypassed with a ferrite-bead-based choke, and a

range of capacitors. A “choke” is preferable to an “inductor” in

this application, since a high-Q inductor will be likely to cause one

or more resonances with the shunt capacitors, potentially

causing problems at or near those frequencies, while a “lossy”

choke will reflect a high impedance over a wide frequency range.

The higher value capacitor, in particular, needs to be chosen

carefully, with special care regarding its ESR. Very good results

can be obtained with multilayer ceramic capacitors (available

from many suppliers) and generally in small outlines (such as the

1210 outline suggested in the schematic shown in Figure 5

which provide good bypass capabilities down to a few mΩ at

1MHz to 2MHz. Other capacitor technologies may also be

suitable (perhaps niobium oxide), but “classic” electrolytic

capacitors frequently have ESR values of above 1Ω, that nullify

any decoupling effect above the 1kHz to 10kHz frequency range.

Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz

region, and 1000pF capacitors in the 100MHz to 200MHz region.

In general, one of the lower value capacitors should be used at

each supply pin on the IC. Figure 5

shows the grounding of the

various capacitors to the pin corresponding to the supply pin.

Although all the ground supplies are tied together, the PCB layout

should be arranged to emulate this arrangement (at least for the

smaller value (high frequency) capacitors), as much as possible.

C Interface

The I

C interface allows access to internal registers used to

configure the SERDES and to obtain status information. A

serializer must be assigned a different address than its

deserializer counterpart if the side channel is used. The upper 5

bits are permanently set to 011 11 and the lower 2 bits

determined by pins as follows:

Thus, 4 SERDES can reside on the same bus. By convention,

when all address pins are tied low, the device address is referred

to as 0x78.

SCL and SDA are open drain to allow multiple devices to share

the bus. If not used, SCL and SDA should be tied to VDD_IO.

01111I2CA1I2CA0R/W

FIGURE 5. POWER SUPPLY BYPASSING

10µF

120Ω

0.1µF

ISL76322

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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

May 6, 2015

FN7611.3

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Exposed Pad

While it is not a required electrical connection, it is

recommended that the exposed pad on the bottom of the

package be soldered to the circuit board. This will ensure that the

full power dissipation of the package can be utilized. The pad

should be connected to ground and not left floating. For best

thermal conductivity, 16 vias should connect the footprint for the

exposed pad on the circuit board to the ground plane. This

connection is not required for basic operation of the chip.

FIGURE 6. LAYOUT FOR THE EXPOSED PAD

COPPER PAD

VIAS

16x

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

ISL76322ARZ

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Serializers & Deserializers - Serdes ISL76322 48L 7X7(PUN CHED AUTO

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New from this manufacturer.

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ISL76322ARZ

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