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Output Rise and Fall Times t
OR
/t
OF
Slew rate control set to min
C
L
= 8pF
1ns
Slew rate control set to max, C
L
= 8pF 4 ns
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency f
IN
650MHz
PCLK_IN Duty Cycle t
IDC
40 50 60 %
Parallel Input Setup Time t
IS
3.5 ns
Parallel Input Hold Time t
IH
1.0 ns
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency f
OUT
650MHz
PCLK_OUT Duty Cycle t
ODC
50 %
PCLK_OUT Period Jitter (rms) t
OJ
Clock randomizer off 0.5 %t
PCLK
PCLK_OUT Spread Width t
OSPRD
Clock randomizer on ±20 %t
PCLK
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
t
DV
Relative to PCLK_OUT,
(Note 9
)
-1.0 5.5 ns
Deserializer Output Latency t
CPD
Inherent in the design 4 9 14 PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time t
PLL
100 µs
REF_CLK to PCLK_OUT Maximum Frequency Offset PCLK_OUT is the
recovered clock
1500 5000 ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit VOD
TR
TXCN = 0x00 650 800 900 mV
P-P
TXCN = 0x0F 900 mV
P-P
TXCN = 0xF0 1100 mV
P-P
TXCN = 0xFF 1300 mV
P-P
HS Differential Output Voltage, Non-Transition Bit VOD
NTR
TXCN = 0x00 650 800 900 mV
P-P
TXCN = 0x0F 900 mV
P-P
TXCN = 0xF0 430 mV
P-P
TXCN = 0xFF 600 mV
P-P
HS Generated Output Common Mode Voltage V
OCM
2.35 V
HS Common Mode Serializer-Deserializer Voltage
Difference
V
CM
10 20 mV
HS Differential Output Impedance R
OUT
80 100 120 Ω
HS Output Latency t
LPD
Inherent in the design 4 7 10 PCLK
HS Output Rise and Fall Times t
R/
t
F
20% to 80% 150 ps
HS Differential Skew t
SKEW
<10 ps
HS Output Random Jitter t
RJ
PCLK_IN = 45MHz 6 ps
rms
HS Output Deterministic Jitter t
DJ
PCLK_IN = 45MHz 25 ps
P-P
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR
= VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX=VDD_P=VDD_AN
= 3.3V, T
A
= +25°C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 10
)TYP
MAX
(Note 10)UNIT
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HIGH SPEED RECEIVER
HS Differential Input Voltage V
ID
75 mV
P-P
HS Generated Input Common Mode Voltage V
ICM
2.32 V
HS Differential Input Impedance R
IN
80 100 120 Ω
HS Maximum Jitter Tolerance 0.50 UI
P-P
I
2
C
I
2
C Clock Rate (on SCL) f
I2C
100 400 kHz
I
2
C Clock Pulse Width (HI or LO) 1.3 µs
I
2
C Clock Low to Data Out Valid 01µs
I
2
C Start/Stop Setup/Hold Time 0.6 µs
I
2
C Data in Setup Time 100 ns
I
2
C Data in Hold Time 100 ns
I
2
C Data out Hold Time 100 ms
NOTES:
8. IDDIO is nominally 50µA and not included in this total as it is dominated by the loading of the parallel pins.
9. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is dependent on the PCLK
frequency and is calculated as follows: 0.5 * f
IN
- t
DV.
.
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR
= VDD_CR = 1.8V, VDD_IO = 3.3V
,
VDD_TX=VDD_P=VDD_AN
= 3.3V, T
A
= +25°C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 10
)TYP
MAX
(Note 10)UNIT
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Timing Diagrams
FIGURE 2. VOD vs TX SETTING
VOD TRANSITION BIT
VOD NON-TRANSITION BIT
BIT BOUNDARY
BIT BOUNDARY
BIT BOUNDARY
VCM
TXP
TXN
VOLTAGE
Tx SETTING
0x0F
0xF0
0xFF
0x00
FIGURE 3. PARALLEL VIDEO INPUT TIMING
1/F
IN
t
IDC
t
IS
t
IH
t
IH
t
IS
SERIALIZER MODE
PCLK_IN
(RISING EDGE
DEFAULT)
VALID DATA VALID DATA VALID DATA
DATA IGNORED DATA IGNORED
RGBA[7:0],
RGBC[7:0]
HSYNC OR VSYNC
(HVSYNCPOL = ‘0’)
DATAEN
(ACTIVE ‘1’ DEFAULT)

ISL76322ARZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Serializers & Deserializers - Serdes ISL76322 48L 7X7(PUN CHED AUTO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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