9397 750 15046 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 26 May 2005 4 of 17
Philips Semiconductors
74ABT16543
16-bit latched transceiver with dual enable; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Pin configuration QFP52
16543
1A2 1B2
1A3 1B3
1A4 1B4
GND 1B5
1A5 1B6
1A6 1B7
1A7 2B0
2A0 2B1
2A1 2B2
2A2 GND
2A3 2B3
2A4 2B4
2A5 2B5
V
CC
V
CC
2A6 1A1
2A7 1A0
GND 1EAB
2EAB 1LEAB
2LEAB 1OEAB
2OEAB 1OEBA
2OEBA 1LEBA
2LEBA 1EBA
2EBA GND
2B7 1B0
2B6 1B1
V
CC
V
CC
001aad034
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
Table 3: Pin description
Symbol Pin Description
1A2 1 1 data input or output 2; A-side
1A3 2 1 data input or output 3; A-side
1A4 3 1 data input or output 4; A-side
GND 4 ground (0 V)
1A5 5 1 data input or output 5; A-side
1A6 6 1 data input or output 6; A-side
1A7 7 1 data input or output 7; A-side
2A0 8 2 data input or output 0; A-side
2A1 9 2 data input or output 1; A-side
2A2 10 2 data input or output 2; A-side
2A3 11 2 data input or output 3; A-side
2A4 12 2 data input or output 4; A-side
2A5 13 2 data input or output 5; A-side
V
CC
14 supply voltage
2A6 15 2 data input or output 6; A-side
9397 750 15046 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 26 May 2005 5 of 17
Philips Semiconductors
74ABT16543
16-bit latched transceiver with dual enable; 3-state
2A7 16 2 data input or output 7; A-side
GND 17 ground (0 V)
2
EAB 18 A-to-B output enable input (active LOW)
2
LEAB 19 A-to-B latch enable input (active LOW)
2
OEAB 20 A-to-B enable input (active LOW)
2
OEBA 21 B-to-A output enable input (active LOW)
2
LEBA 22 B-to-A latch enable input (active LOW)
2
EBA 23 B-to-A enable input (active LOW)
2B7 24 2 data input or output 7; B-side
2B6 25 2 data input or output 6; B-side
V
CC
26 supply voltage
2B5 27 2 data input or output 5; B-side
2B4 28 2 data input or output 4; B-side
2B3 29 2 data input or output 3; B-side
GND 30 ground (0 V)
2B2 31 2 data input or output 2; B-side
2B1 32 2 data input or output 1; B-side
2B0 33 2 data input or output 0; B-side
1B7 34 1 data input or output 7; B-side
1B6 35 1 data input or output 6; B-side
1B5 36 1 data input or output 5; B-side
1B4 37 1 data input or output 4; B-side
1B3 38 1 data input or output 3; B-side
1B2 39 1 data input or output 2; B-side
V
CC
40 positive supply voltage
1B1 41 1 data input or output 1; B-side
1B0 42 1 data input or output 0; B-side
GND 43 ground (0 V)
1
EBA 44 B-to-A output enable input (active LOW)
1
LEBA 45 B-to-A latch enable input (active LOW)
1
OEBA 46 B-to-A enable input (active LOW)
1
OEAB 47 A-to-B output enable input (active LOW)
1
LEAB 48 A-to-B latch enable input (active LOW)
1
EAB 49 A-to-B enable input (active LOW)
1A0 50 1 data input or output 0; A-side
1A1 51 1 data input or output 1; A-side
V
CC
52 supply voltage
Table 3: Pin description
…continued
Symbol Pin Description
9397 750 15046 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 04 — 26 May 2005 6 of 17
Philips Semiconductors
74ABT16543
16-bit latched transceiver with dual enable; 3-state
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or
nEBA;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or
nEBA;
X = don t care;
Z = high-impedance off state;
= LOW-to-HIGH transition;
NC= no change.
7.2 Description
The 74ABT16543 contains two sets of eight D-type latches, with separate control pins for
each set. Using data flow from A to B as an example, when the A-to-B enable (nEAB)
input and the A-to-B latch enable (nLEAB) input are LOW the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the nLEAB signal puts the A data into the
latches where it is stored and the B outputs no longer change with the A inputs. With
nEAB and nOEAB both LOW, the 3-state B output buffers are active and display the data
present at the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs.
Table 4: Function table
[1]
Input Output Status
nOEAB or
n
OEBA
nEAB or
n
EBA
nLEAB or
n
LEBA
nAx or nBx nBx or nAx
HXXXZdisabled
X H X X Z disabled
L L h Z disabled + latch
L L I Z disabled + latch
LL h H latch + display
LL I L latch + display
L L L H H transparent
LLLLLtransparent
L L H X NC hold

74ABT16543BB,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 5.5V 52QFP
Lifecycle:
New from this manufacturer.
Delivery:
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