MAX1644
2A, Low-Voltage, Step-Down Regulator with
Synchronous Rectification and Internal Switches
6 _______________________________________________________________________________________
_______________Detailed Description
The MAX1644 synchronous, current-mode, constant-off-
time, PWM DC-DC converter steps down input voltages
of +3V to +5.5V to a preset output voltage of either +3.3V
or +2.5V, or to an adjustable output voltage from +1.1V
to V
IN
. The device delivers up to 2A of continuous load
current. Internal switches composed of a 0.1Ω PMOS
power switch and a 0.1Ω NMOS synchronous-rectifier
switch improve efficiency, reduce component count, and
eliminate the need for an external Schottky diode.
The MAX1644 optimizes performance by operating in
constant-off-time mode under heavy loads and in
Maxim’s proprietary Idle Mode under light loads. A sin-
gle resistor-programmable constant-off-time control
sets switching frequencies up to 350kHz, allowing the
user to optimize performance trade-offs in efficiency,
switching noise, component size, and cost. Under low-
dropout conditions, the device operates in a 100%
duty-cycle mode, where the PMOS switch remains per-
manently on. Idle Mode enhances light-load efficiency
by skipping cycles, thus reducing transition and gate-
charge losses.
When power is drawn from a regulated supply, constant-
off-time PWM architecture essentially provides constant-
frequency operation. This architecture has the inherent
advantage of quick response to line and load transients.
The MAX1644’s current-mode, constant-off-time PWM
architecture regulates the output voltage by changing
the PMOS switch on-time relative to the constant off-
time. Increasing the on-time increases the peak induc-
tor current and the amount of energy transferred to the
load per pulse.
Modes of Operation
The current through the PMOS switch determines the
mode of operation: constant-off-time mode (for load
currents greater than 0.2A) or Idle Mode (for load cur-
rents less than 0.2A). Current sense is achieved
through a proprietary architecture that eliminates cur-
rent-sensing I
2
R losses.
Constant-Off-Time Mode
Constant-off-time operation occurs when the current
through the PMOS switch is greater than the Idle Mode
threshold current (0.4A, which corresponds to a load
current of 0.2A). In this mode, the regulation compara-
tor turns the PMOS switch on at the end of each off-
time, keeping the device in continuous-conduction
mode. The PMOS switch remains on until the output is
in regulation or the current limit is reached. When the
PMOS switch turns off, it remains off for the pro-
grammed off-time (t
OFF
). If the output falls dramatically
out of regulation—approximately V
FB
/ 4—the PMOS
switch remains off for approximately four times t
OFF
.
The NMOS synchronous rectifier turns on shortly after
the PMOS switch turns off, and it remains on until short-
ly before the PMOS switch turns back on.
Idle Mode
Under light loads, the device improves efficiency by
switching to a pulse-skipping Idle Mode. Idle Mode
operation occurs when the current through the PMOS
switch is less than the Idle Mode threshold current. Idle
Mode forces the PMOS to remain on until the current
through the switch reaches 0.4A, thus minimizing the
unnecessary switching that degrades efficiency under
light loads. In Idle Mode, the device operates in discon-
tinuous conduction. Current-sense circuitry monitors the
current through the NMOS synchronous switch, turning it
off before the current reverses. This prevents current
from being pulled from the output filter through the
inductor and NMOS switch to ground. As the device
switches between operating modes, no major shift in cir-
cuit behavior occurs.
100% Duty-Cycle Operation
When the input voltage drops near the output voltage,
the duty cycle increases until the PMOS MOSFET is on
continuously. The dropout voltage in 100% duty cycle
is the output current multiplied by the on-resistance of
the internal PMOS switch and parasitic resistance in the
inductor. The PMOS switch remains on continuously as
long as the current limit is not reached.
Shutdown
Drive SHDN to a logic-level low to place the MAX1644
in low-power shutdown mode and reduce supply cur-
rent to less than 1µA. In shutdown, all circuitry and
internal MOSFETs turn off, and the LX node becomes
high impedance. Drive SHDN to a logic-level high or
connect to V
CC
for normal operation.
Summing Comparator
Three signals are added together at the input of the
summing comparator (Figure 1): an output voltage error
signal relative to the reference voltage, an integrated
output voltage error correction signal, and the sensed
PMOS switch current. The integrated error signal is pro-
vided by a transconductance amplifier with an external
capacitor at COMP. This integrator provides high DC
accuracy without the need for a high-gain amplifier.
Connecting a capacitor at COMP modifies the overall
loop response (see the Integrator Amplifier section).
