24FC515-I/P Datasheet 24LC515-I/SM, 24LC515T-I/SM, 24AA515-I/SM | P4-P6

24AA515/24LC515/24FC515

FIGURE 1-1: BUS TIMING DATA

(unprotected)

(protected)

SCL

SDA

OUT

24AA515/24LC515/24FC515

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 A0, A1 Chip Address Inputs

The A0, A1 inputs are used by the 24XX515 for multiple

device operations. The levels on these inputs are

compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

Up to four devices may be connected to the same bus

by using different Chip Select bit combinations. In most

applications, the chip address inputs A0 and A1 are

hard-wired to logic ‘0’ or logic ‘1’. For applications in

which these pins are controlled by a microcontroller or

other programmable device, the chip address pins

must be driven to logic ‘0’ or logic ‘1’ before normal

device operation can proceed.

2.2 A2 Chip Address Input

The A2 input is non-configurable Chip Select. This pin

must be tied to V

CC in order for this device to operate.

2.3 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open-

drain terminal, therefore, the SDA bus requires a pull-

up resistor to V

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

400kHz and 1MHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.4 Serial Clock (SCL)

This input is used to synchronize the data transfer from

and to the device.

2.5 Write-Protect (WP)

This pin must be connected to either VSS or VCC. If tied

to V

SS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24XX515 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX515 works as a slave. Both master and slave can

operate as a transmitter or receiver, but the master

device determines which mode is activated.

Name PDIP SOIJ Function

A0 1 1 User Configurable Chip Select

A1 2 2 User Configurable Chip Select

A2 3 3 Non-Configurable Chip Select.

This pin must be hard wired to

logical 1 state (V

CC). Device

will not operate with this pin

left floating or held to logical 0

SS).

VSS 4 4 Ground

SDA 5 5 Serial Data

SCL 6 6 Serial Clock

WP 7 7 Write-Protect Input

CC 8 8 +1.7 to 5.5V (24AA515)

+2.5 to 5.5V (24LC515)

+2.5 to 5.5V (24FC515)

24AA515/24LC515/24FC515

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX515) will leave the data line high to enable

the master to generate the Stop condition.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24XX515 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress, however, the

control byte that is being polled must

match the control byte used to initiate the

write cycle.

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

Start

Condition

SCL

SDA

(A) (B) (D) (D) (C) (A)

SCL

987654321123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this

point so the Transmitter can continue

sending data.

Data from transmitter

SDA

Acknowledge

Bit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

24FC515-I/P

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EEPROM 64kx8 64B 1.8V HISpd

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24FC515-I/P

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