© 2008 Microchip Technology Inc. DS21673G-page 7
24AA515/24LC515/24FC515
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX515, this is set as ‘1010’ binary for read and write
operations. The next bit of the control byte is the block
select bit (B0). This bit acts as the A15 address bit for
accessing the entire array. The next two bits of the
control byte are the Chip Select bits (A1, A0). The Chip
Select bits allow the use of up to four 24XX515 devices
on the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A1
and A0 pins for the device to respond. These bits are in
effect the two Most Significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected, and when set to a ‘0’, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX515 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W
bit, the 24XX515 will select a read or
write operation.
This device has an internal addressing boundary
limitation that is divided into two segments of 256K bits.
Block select bit ‘B0’ is used in place of address bit
location ‘A15’ to control access to each segment.
FIGURE 5-1: CONTROL BYTE
FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A1, A0 can be used to expand the
contiguous address space for up to 2 Mbit by adding up
to four 24XX515’s on the same bus. In this case,
software can use A0 of the control byte
as address bit
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
256K bits. The block select bit ‘B0’ controls access to
each “half” rather than address bit location A15.
Sequential read operations are limited to 256K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010B0 A1 A0SACKR/W
Control Code
Chip
Slave Address
Acknowledge Bit
Start Bit
Read/Write
Bit
Select
Bits
Block
Select
Bit
1010
B
0
A
1
A
0
R/W x
A
11
A
10
A
9
A
7
A
0
A
8
••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
Bits
X = “don’t care” bit
A
13
A
14
Block
Select
Bit
24AA515/24LC515/24FC515
DS21673G-page 8 © 2008 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the block select (one bit) the
Chip Select (two bits), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle. There-
fore, the next byte transmitted by the master is the
high-order byte of the word address and will be written
into the Address Pointer of the 24XX515. The next byte
is the Least Significant Address Byte. After receiving
another Acknowledge signal from the 24XX515, the
master device will transmit the data word to be written
into the addressed memory location. The 24XX515
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX515 will not generate
Acknowledge signals as long as the control byte being
polled matches the control byte that was used to initiate
the write (Figure 6-1). If an attempt is made to write to
the array with the WP pin held high, the device will
acknowledge the command but no write cycle will
occur, no data will be written, and the device will
immediately accept a new command. After a byte Write
command, the internal address counter will point to the
address location following the one that was just written.
6.2 Page Write
The write control byte, word address, and the first data
byte are transmitted to the 24XX515 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 63 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the six lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-FFFF) when the pin is tied to V
CC. If tied to
V
SS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1) Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
© 2008 Microchip Technology Inc. DS21673G-page 9
24AA515/24LC515/24FC515
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = “don’t care” bit
S 1010 0
B
0
A
1
A
0
P
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 63
A
C
K
X = “don’t care” bit
S 1010 0
B
0
A
1
A
0
P

24FC515-I/P

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 64kx8 64B 1.8V HISpd
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union