HEF4040B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 3 of 13
NXP Semiconductors
HEF4040B-Q100
12-stage binary ripple counter
6. Pinning information
6.1 Pinning
Fig 3. Timing diagram
001aad587
1 2 4 8 16 32 64 128 256 512 1024 2048 4096
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Fig 4. Pin configuration
+()%4
4
9
''
4
4
4
4
4
4
4
4
4
05
4
&3
9
6
6
4
DDD







HEF4040B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 4 of 13
NXP Semiconductors
HEF4040B-Q100
12-stage binary ripple counter
6.2 Pin description
7. Limiting values
[1] For SO16 package: P
tot
derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 2. Pin description
Symbol Pin Description
V
SS
8 ground supply voltage
Q0 to Q11 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 parallel output
CP
10 clock input (HIGH-to-LOW edge-triggered)
MR 11 master reset input (active HIGH)
V
DD
16 supply voltage
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +18 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
DD
+ 0.5 V - 10 mA
V
I
input voltage 0.5 V
DD
+ 0.5 V
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
DD
+ 0.5 V - 10 mA
I
I/O
input/output current - 10 mA
I
DD
supply current - 50 mA
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature 40 +85 C
P
tot
total power dissipation
[1]
-500mW
P power dissipation per output - 100 mW
Table 4. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3 - 15 V
V
I
input voltage 0 - V
DD
V
T
amb
ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate V
DD
= 5V --3.75ms/V
V
DD
= 10 V --0.5ms/V
V
DD
= 15 V --0.08ms/V
HEF4040B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 5 of 13
NXP Semiconductors
HEF4040B-Q100
12-stage binary ripple counter
9. Static characteristics
Table 5. Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= 25 C T
amb
= 85 C Unit
Min Max Min Max Min Max
V
IH
HIGH-level input voltage I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level input voltage I
O
< 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
V
OH
HIGH-level output voltage I
O
< 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level output voltage I
O
< 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
I
OH
HIGH-level output current V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
V
O
= 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
V
O
= 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
V
O
= 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
I
OL
LOW-level output current V
O
= 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
V
O
= 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
V
O
= 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
I
LI
input leakage current 15 V - 0.3 - 0.3 - 1.0 A
I
DD
supply current I
O
= 0 A 5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A
C
I
input capacitance - - - - 7.5 - - pF

HEF4040BT-Q100J

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter ICs 12-stage binary ripple counter
Lifecycle:
New from this manufacturer.
Delivery:
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