MPC9774
MOTOROLA TIMING SOLUTIONS4
Table 4. Function Table (QFB)
VCO_SEL FSEL_B1 FSEL_B0 QFB
0 0 0 VCO ÷ 8
0 0 1 VCO ÷ 16
0 1 0 VCO ÷ 12
0 1 1 VCO ÷ 24
1 0 0 VCO ÷ 16
1 0 1 VCO ÷ 32
1 1 0 VCO ÷ 24
1 1 1 VCO ÷ 48
Table 5. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
÷ 2 V
MM ESD protection (Machine Model) 200 V
HBM ESD protection (Human Body Model) 2000 V
LU Latch-Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 12 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 6. Absolute Maximum Ratings
a
Symbol Characteristics Min Max Unit Condition5
V
CC
Supply Voltage -0.3 3.9 V
V
IN
DC Input Voltage -0.3 V
CC
+ 0.3 V
V
OUT
DC Output Voltage -0.3 V
CC
+ 0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage Temperature -65 125 °C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 7. DC Characteristics (V
CC
= 3.3V ± 5%, T
A
= 0°C to +70°C)
Symbol Characteristics Min Typ Max Unit Condition
V
CC_PLL
PLL Supply Voltage 3.02 V
CC
V LVCMOS
V
IH
Input High Voltage 2.0 V
CC
+ 0.3 V LVCMOS
V
IL
Input Low Voltage 0.8 V LVCMOS
V
OH
Output High Voltage 2.4 V I
OH
= -24 mA
a
V
OL
Output Low Voltage 0.55
0.30
V
V
I
OL
= 24 mA
I
OL
= 12 mA
Z
OUT
Output Impedance 14 - 17
I
IN
Input Current
b
±200 µA V
IN
= V
CC
or GND
I
CC_PLL
Maximum PLL Supply Current 5.0 7.5 mA V
CC_PLL
Pin
I
CCQ
Maximum Quiescent Supply Current 8.0 mA All V
CC
Pins
a. The MPC9774 is capable of driving 50transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50 series terminated transmission lines.
b. Inputs have pull-down or pull-up resistors affecting the input current.
MPC9774
TIMING SOLUTIONS 5 MOTOROLA
Table 8. AC Characteristics (V
CC
= 3.3V ± 5%, T
A
= 0°C to +70°C)
a
Symbol Characteristics Min Typ Max Unit Condition
f
REF
Input Reference Frequency ÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
Input Reference Frequency in PLL Bypass Mode
b
25.0
16.6
12.5
8.33
6.25
4.16
62.5
41.6
31.25
20.83
15.625
10.41
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
f
VCO
VCO Frequency Range
c
200 500 MHz
f
MAX
Output Frequency ÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
50.0
25.0
16.6
12.5
8.33
125.0
62.5
41.6
31.25
20.83
MHz
MHz
MHz
MHz
MHz
PLL locked
t
PW,MIN
Input Reference Pulse Width
d
2.0 ns
t
R
, t
F
CCLKx Input Rise/Fall Time 1.0 ns 0.8 to 2.0V
t
(
)
Propagation Delay (static phase offset)
e
CCLKx to FB_IN (FB=÷8 and f
REF
=50 MHz) -250 +100 ps PLL locked
t
SK(O)
Output-to-output Skew
f
within QA bank
within QB bank
within QC bank
any output
100
125
100
175
ps
ps
ps
ps
DC Output Duty Cycle 47 50 53 %
t
R
, t
F
Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4V
t
PLZ,
HZ
Output Disable Time 10 ns
t
PZL
Output Enable Time 10 ns
t
JIT(CC)
Cycle-to-cycle Jitter
g
90 ps
t
JIT(PER)
Period Jitter
f
90 ps
t
JIT(
)
I/O Phase Jitter RMS (1 σ)
h
FB=÷8
FB=÷12
FB=÷16
FB=÷24
FB=÷32
FB=÷48
15
49
18
22
26
34
ps
ps
ps
ps
ps
ps
BW PLL Closed Loop Bandwidth
i
FB=÷8
FB=÷12
FB=÷16
FB=÷24
FB=÷32
FB=÷48
0.50 - 1.80
0.30 - 1.00
0.25 - 0.70
0.17 - 0.40
0.12 - 0.30
0.07 - 0.20
MHz
MHz
MHZ
MHz
MHz
MHz
t
LOCK
Maximum PLL Lock Time 10 ms
a AC characteristics apply for parallel output termination of 50 to V
TT
.
b In bypass mode, the MPC9774 divides the input reference clock.
c The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): f
REF
=f
VCO
÷(M VCO_SEL).
d Calculation of reference duty cycle limits: DC
REF,MIN
= t
PW,MIN
f
REF
100% and DC
REF,MAX
= 100% - DC
REF,
MIN.
E.g. at f
REF
=62.5 MHz
the input duty cycle range is 12.5% < DC < 87.5%.
e Static phase offset depends on the reference frequency: t
(
)
= +50 ps ± (1÷(120 f
REF
)) for any reference frequency.
f See application section for part-to-part skew calculation.
g Valid for all outputs at the same fequency.
h I/O jitter for f
VCO
=400 MHz. See application section for I/O jitter at other frequencies and for a jitter calculation for confidence factors other
than 1 s.
i -3 dB point of PLL transfer characteristics.
MPC9774
MOTOROLA TIMING SOLUTIONS6
APPLICATIONS INFORMATION
MPC9774 Configurations
Configuring the MPC9774 amounts to properly configuring
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
÷
÷
÷




÷

where f
REF
is the reference frequency of the selected input
clock source (CCLKO or CCLK1), M is the PLL feedback
divider and N is a output divider. M is configured by the
FSEL_FB[0:1] and N is individually configured for each
output bank by the FSEL_A, FSEL_B and FSEL_C inputs.
The reference frequency f
REF
and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. f
REF
and M must be configured to match the VCO
frequency range of 200 to 500 MHz in order to achieve stable
PLL operation:
f
VCO,MIN
(f
REF
VCO_SEL M) f
VCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two
or a divide-by-four and can be used to situate the VCO into
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio. The output frequency for each
bank can be derived from the VCO frequency and the output
divider:
f
QA[4:0]
= f
VCO
÷ (VCO_SEL N
A
)
f
QB[4:0]
= f
VCO
÷ (VCO_SEL N
B
)
f
QC[3:0]
= f
VCO
÷ (VCO_SEL N
C
)
Table 9. MPC9774 Divider
Divider Function VCO_SEL Values
M PLL feedback
÷2 8, 12, 16, 24
FSEL_FB[0:1]
÷4 16, 24, 32, 48
N
A
Bank A Output
÷2 4, 8
A
p
Divider FSEL_A
÷4 8, 16
N
B
Bank B Output
÷2 4, 8
B
p
Divider FSEL_B
÷4 8, 16
N
C
Bank C Output
÷2 8, 12
C
p
Divider FSEL_C
÷4 16, 24
Table 9 shows the various PLL feedback and output
dividers. The output dividers for the three output banks allow
the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1
frequency ratios. Figure 3 and Figure 4 display example
configurations for the MPC9774:
Figure 3. Example Configuration Figure 4. Example Configuration
MPC9774
  
 
 
  
 
MPC9774 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL = ÷2, M = 12, N
A
=
2, N
B
= 4, N
C
= 4, f
VCO
= 500 MHz).
Frequency range Min Max
Input 8.33 MHz 20.83 MHz
QA outputs 50 MHz 125 MHz
QB outputs 25 MHz 62.5 MHz
QC outputs 25 MHz 62.5 MHz














MPC9774
  
 
 
  
 
MPC9774 example configuration (feedback of
QFB = 25 MHz, VCO_SEL = ÷2, M = 8, N
A
= 2,
N
B
= 4, N
C
= 6, f
VCO
= 400 MHz).
Frequency range Min Max
Input 20 MHz 48 MHz
QA outputs 50 MHz 120 MHz
QB outputs 50 MHz 120 MHz
QC outputs 100 MHz 200 MHz















MPC9774AE

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Clock Generators & Support Products 3.3V 125MHz Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet