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MPC9774AE

P1-P3P4-P6P7-P9P10-P12
MPC9774
TIMING SOLUTIONS 7 MOTOROLA
Using the MPC9774 in zero-delay applications
Nested clock trees are typical applications for the
MPC9774. Designs using the MPC9774 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback of the
MPC9774 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC9774 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9774 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
t
SK(PP)
= t
(
∅
)
+ t
SK(O)
+ t
PD,
LINE(FB)
+ t
JIT(
∅
)
CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 5. MPC9774 max. device-to-device skew


∅
±t


∅

∅

∅
±t


 










Due to the statistical nature of I/O jitter a rms value (1 σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 10.
Table 10. Confidence factor CF
CF Probability of clock edge within the distribution
± 1s 0.68268948
± 2s 0.95449988
± 3s 0.99730007
± 4s 0.99993663
± 5s 0.99999943
± 6s 0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 6 and Figure 7 to predict a
maximum I/O jitter and the specified t
(
∅
)
parameter relative to
the input reference frequency results in a precise timing
performance analysis.
In the following example calculation a I/O jitter confidence
factor of 99.7% (± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of -470 ps to +320 ps relative to CCLK (PLL
feedback = B8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 15 ps rms max., static
phase offset t
(
∅
)
= –250 ps to +100 ps):
t
SK(PP)
= [–250 ps...+100 ps] + [–175 ps...175 ps] +
[(15 ps
⋅ –3)...(15 ps ⋅ 3)] + t
PD,
LINE(FB)
t
SK(PP)
= [–470 ps...+320 ps] + t
PD,
LINE(FB)
Figure 6. MPC9774 I/O Jitter
Figure 7. MPC9774 I/O Jitter
  
      






÷
÷
      
    

∅
÷
  
      





÷
÷
÷
      
    

∅


MPC9774
MOTOROLA TIMING SOLUTIONS8
Driving Transmission Lines
The MPC9774 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to V
CC
÷ 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9774 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 8 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9774 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
Ω




Ω
Ω

Ω




Ω
Ω

Ω
Ω

The waveform plots in Figure 9 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9774 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9774. The output waveform in Figure 9 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
V
L
= V
S
( Z
0
÷ (R
S
+ R
0
+ Z
0
))
Z
0
= 50Ω || 50Ω
R
S
= 36Ω || 36Ω
R
0
= 14Ω
V
L
= 3.0 ( 25 ÷ (18 + 17 + 25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Figure 9. Single versus Dual Waveforms
 







  





Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 10 “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
Figure 10. Optimized Dual Line Termination
Ω



Ω
Ω
Ω
Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
MPC9774
TIMING SOLUTIONS 9 MOTOROLA
Power Supply Filtering
The MPC9774 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL power supply impacts the device
characteristics, for instance I/O jitter. The MPC9774 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device.The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9774. Figure 11 illustrates a typical
power supply filter scheme. The MPC9774 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor R
F
. From the data sheet
the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 5 mA (7.5 mA maximum),
assuming that a minimum of 3.02 V (VCC_PLL, min) must be
maintained on the VCC_PLL pin. The resistor R
F
shown in
Figure 11 must have a resistance of 5-15Ω to meet the
voltage drop criteria.
The minimum values for RF and the filter capacitor C
F
are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 11, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
Figure 11. V
CC_PLL
Power Supply Filter


MPC9774
 
Ω
 

 µ
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9774 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Figure 12. CCLK MPC9774 AC test reference


W
Ω
Ω
Ω
Ω
 


P1-P3P4-P6P7-P9P10-P12

MPC9774AE

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Clock Generators & Support Products 3.3V 125MHz Clock Generator
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