AT91SAM9M10C-CU-999 Datasheet AT91SAM9M10C-CU-999, AT91SAM9M10B-CU | P16-P18

SAM9M10 [SUMMARY]

6355ES–ATARM–12-Mar-13

6. Processor and Architecture

6.1 ARM926EJ-S Processor

z RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration

z Two Instruction Sets

z ARM High-performance 32-bit Instruction Set

z Thumb High Code Density 16-bit Instruction Set

z DSP Instruction Extensions

z 5-Stage Pipeline Architecture:

z Instruction Fetch (F)

z Instruction Decode (D)

z Execute (E)

z Data Memory (M)

z Register Write (W)

z 32-KByte Data Cache, 32-KByte Instruction Cache

z Virtually-addressed 4-way Associative Cache

z Eight words per line

z Write-through and Write-back Operation

z Pseudo-random or Round-robin Replacement

z Write Buffer

z Main Write Buffer with 16-word Data Buffer and 4-address Buffer

z DCache Write-back Buffer with 8-word Entries and a Single Address Entry

z Software Control Drain

z Standard ARM v4 and v5 Memory Management Unit (MMU)

z Access Permission for Sections

z Access Permission for large pages and small pages can be specified separately for each quarter of the

page

z 16 embedded domains

z Bus Interface Unit (BIU)

z Arbitrates and Schedules AHB Requests

z Separate Masters for both instruction and data access providing complete Matrix system flexibility

z Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface

z On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)

z TCM Interface

SAM9M10 [SUMMARY]

6355ES–ATARM–12-Mar-13

6.2 Bus Matrix

z 12-layer Matrix, handling requests from 11 masters

z Programmable Arbitration strategy

z Fixed-priority Arbitration

z Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master

z Burst Management

z Breaking with Slot Cycle Limit Support

z Undefined Burst Length Support

z One Address Decoder provided per Master

z Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for

internal flash boot, one after remap

z Boot Mode Select

z Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0

z Selection is made by General purpose NVM bit sampled at reset

z Remap Command

z Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)

z Allows Handling of Dynamic Exception Vectors

6.2.1 Matrix Masters

The Bus Matrix of the SAM9M10 manages Masters, thus each master can perform an access concurrently with others,

depending on whether the slave it accesses is available.

Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing,

all the masters have the same decodings.

Table 6-1. List of Bus Matrix Masters

Master 0 ARM926

™

Instruction

Master 1 ARM926 Data

Master 2 Peripheral DMA Controller (PDC)

Master 3 USB HOST OHCI

Master 4 DMA

Master 5 DMA

Master 6 ISI Controller DMA

Master 7 LCD DMA

Master 8 Ethernet MAC DMA

Master 9 USB Device High Speed DMA

Master 10 USB Host High Speed EHCI DMA

Master 11 Video Decoder

SAM9M10 [SUMMARY]

6355ES–ATARM–12-Mar-13

6.2.2 Matrix Slaves

Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.

6.2.3 Masters to Slaves Access

All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access

from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-”

in the following tables.

The four DDR ports are connected differently according to the application device.

The user can disable the Video Decoder in the Video Mode Configuration Register (bit VDEC_SEL) in the Chip

Configuration User Interface.

z When the Video Decoder is not enabled (VDEC_SEL=0), the ARM instruction and data are respectively connected to

DDR Port 0 and DDR Port 1. The other masters share DDR Port 2 and DDR Port 3.

z When the Video Decoder is enabled (VDEC_SEL=1), DDR Port 0 is dedicated to the video controller, and DDR Port 1

to the LCD controller. The remaining masters share DDR Port 2 and DDR Port 3.

Table 6-2. List of Bus Matrix Slaves

Slave 0 Internal SRAM

Slave 1

Internal ROM

USB OHCI

USB EHCI

UDP High Speed RAM

LCD User Interface

Video Decoder

Slave 2 DDR Port 0

Slave 3 DDR Port 1

Slave 4 DDR Port 2

Slave 5 DDR Port 3

Slave 6 External Bus Interface

Slave 7 Internal Peripherals

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P55

AT91SAM9M10C-CU-999

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Microchip Technology / Atmel

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Microprocessors - MPU BGAGREENIND TEMPMRL

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AT91SAM9M10C-CU-999

AT91SAM9M10C-CU-999

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