27
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
z Static Memory Controller
z DDR2/SDRAM Controller
z SLC Nand Flash ECC Controller
z Additional logic for NAND Flash
and CompactFlash
TM
z Optional Full 32-bit External Data Bus
z Up to 26-bit Address Bus (up to 64MBytes linear per chip select)
z Up to 6 chip selects, Configurable Assignment:
z Static Memory Controller on NCS0
z DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
z Static Memory Controller on NCS2
z Static Memory Controller on NCS3, Optional NAND Flash support
z Static Memory Controller on NCS4 - NCS5, Optional CompactFlash
M
support
7.3.2.1 Static Memory Controller
z 8-, 16- or 32-bit Data Bus
z Multiple Access Modes supported
z Byte Write or Byte Select Lines
z Asynchronous read in Page Mode supported (4- up to 32-byte page size)
z Multiple device adaptability
z Control signals programmable setup, pulse and hold time for each Memory Bank
z Multiple Wait State Management
z Programmable Wait State Generation
z External Wait Request
z Programmable Data Float Time
z Slow Clock mode supported
7.3.2.2 DDR2/SDR Controller
z Supports DDR2/LPDDR2, SDR-SDRAM and LPSDR
z Numerous Configurations Supported
z 2K, 4K, 8K, 16K Row Address Memory Parts
z SDRAM with Four Internal Banks
z SDR-SDRAM with 16- or 32- bit Data Path
z DDR2/LPDDR with 16- bit Data Path
z One Chip Select for SDRAM Device (256 Mbyte Address Space)
z Programming Facilities
z Multibank Ping-pong Access (Up to 4 Banks Opened at Same Time = Reduces Average Latency of
Transactions)
z Timing Parameters Specified by Software
z Automatic Refresh Operation, Refresh Rate is Programmable
z Automatic Update of DS, TCR and PASR Parameters (LPSDR)
z Energy-saving Capabilities
z Self-refresh, Power-down and Deep Power Modes Supported
z SDRAM Power-up Initialization by Software
z CAS Latency of 2, 3 Supported
z Auto Precharge Command Not Used
z SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
z Clock Frequency Change in Precharge Power-down Mode Not Supported