NB7VQ14MMNG Datasheet NB7VQ14MMNHTBG, NB7VQ14MMNG, NB7VQ14MMNTXG | P1-P3

December, 2010 − Rev. 0

1 Publication Order Number:

NB7VQ14M/D

NB7VQ14M

1.8V/2.5V/3.3V 8GHz /

14Gbps Differential 1:4

Clock / Data CML Fanout

Buffer

w/ Selectable Input

Equalizer

Multi−Level Inputs w/ Internal Termination

Description

The NB7VQ14M is a high performance differential 1:4 CML fanout

buffer with a selectable Equalizer receiver. When placed in series with

a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the

NB7VQ14M inputs will compensate the degraded signal transmitted

across a FR4 PCB backplane or cable interconnect and output four

identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V

power supply. Therefore, the serial data rate is increased by reducing

Inter−Symbol Interference (ISI) caused by losses in copper

interconnect or long cables. The EQualizer ENable pin (EQEN)

allows the IN/IN inputs to either flow through or bypass the Equalizer

section. Control of the Equalizer function is realized by setting EQEN;

When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When

EQEN is set High, the IN/IN inputs flow through the Equalizer. The

default state at start−up is LOW. As such, NB7VQ14M is ideal for

SONET, GigE, Fiber Channel, Backplane and other Clock/Data

distribution applications.

The differential inputs incorporate internal 50 W termination

resistors that are accessed through the VT pin. This feature allows the

NB7VQ14M to accept various logic level standards, such as LVPECL,

CML or LVDS. The 1:4 fanout design was optimized for low output

skew applications.

The NB7VQ14M is a member of the GigaComm™ family of high

performance clock products.

Features

• Input Data Rate > 14 Gb/s, Typical

• Input Clock Frequency > 8 GHz, Typical

• 165 ps Typical Propagation Delay

• 30 ps Typical Rise and Fall Times

• < 15 ps Maximum Output Skew

• < 0.8 ps Maximum RMS Clock Jitter

• < 10 ps pp of Data Dependent Jitter

• Differential CML Outputs, 400 mV Peak−to−Peak, Typical

• Selectable Input Equalization

• Operating Range: V

= 1.71 V to 3.6 V with GND = 0 V

• Internal Input Termination Resistors, 50 W

• −40°C to +85°C Ambient Operating Temperature

• These are Pb−Free Devices

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

QFN−16

MN SUFFIX

CASE 485G

NB7V

Q14M

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

SIMPLIFIED BLOCK DIAGRAM

NB7VQ14M

http://onsemi.com

Figure 1. Detailed Block Diagram of NB7VQ14M

EQEN

(Equalizer Enable)

Multi−Level Inputs

LVPECL, LVDS, CML

CML Outputs

50 W

75 kW

2:1

MUX

VREFAC

GND

NB7VQ14M

http://onsemi.com

EQEN Q3 Q3 V

GND Q0 Q0 V

VREFAC

5678

16 15 14 13

NB7VQ14M

Exposed Pad (EP)

Figure 2. QFN−16 Pinout (Top View)

Table 1. EQUALIZER ENABLE FUNCTION

EQEN Function

0 IN / IN Inputs By−pass the Equalizer section

1 Inputs flow through the Equalizer

Table 2. PIN DESCRIPTION

Pin Name I/O Description

1 IN LVPECL, CML,

LVDS Input

Non−inverted Differential Input. Note 1.

2 VT

Internal 100 W Center−tapped Termination Pin for IN / IN

3 VREFAC Output Voltage Reference for Capacitor−Coupled Inputs, only

4 IN LVPECL, CML,

LVDS Input

Inverted Differential Input. Note 1.

5 EQEN LVCMOS Input Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor)

6 Q3 CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to V

7 Q3 CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V

8 VCC − Positive Supply Voltage

9 Q2 CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to V

10 Q2 CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V

11 Q1 CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to V

12 Q1 CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V

13 VCC − Positive Supply Voltage

14 Q0 CML Output

Inverted Differential Output. Typically Terminated with 50 W Resistor to V

15 Q0 CML Output

Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V

16 GND − Negative Supply Voltage

− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for

improved heat transfer out of package. The exposed pad must be attached to a heat−sinking

conduit. The pad is electrically connected to the die, and must be electrically and thermally con-

nected to GND on the PC board.

1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal

is applied on IN / IN input, then, the device will be susceptible to self−oscillation.

2. All VCC and GND pins must be externally connected to a power supply for proper operation.

P1-P3 P4-P6 P7-P9 P10-P10

NB7VQ14MMNG

Mfr. #:

Buy NB7VQ14MMNG

Manufacturer:

ON Semiconductor

Description:

Clock Buffer 1.8/2.5/3.3V FANOUT

Lifecycle:

New from this manufacturer.

Delivery:

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NB7VQ14MMNG

NB7VQ14MMNG

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