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Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200V
R
PD
EQEN Input Pulldown Resistor
75 kW
Moisture Sensitivity (Note 3) 16QFN Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 210
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply Core GND = 0 V 4.0 V
V
IO
Positive Input/Output Voltage GND = 0 V 0.5 to V
CC
+
0.5
V
V
INPP
Differential Input Voltage |IN IN| 1.89 V
I
IN
Input Current Through R
T
(50 W Resistor)
$40 mA
I
OUT
Output Current Through R
T
(50 W Resistor)
$40 mA
I
VFREFAC
VREFAC Sink/Source Current $1.5 mA
T
A
Operating Temperature Range 16 QFN 40 to +85
°C
T
stg
Storage Temperature Range 65 to +150
°C
θ
JA
Thermal Resistance (JunctiontoAmbient) (Note 4) 0 lfpm
500 lfpm
16 QFN
16 QFN
42
35
°C/W
°C/W
θ
JC
Thermal Resistance (JunctiontoCase) (Note 4) 16 QFN 4
°C/W
T
sol
Wave Solder PbFree 265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, MULTILEVEL INPUTS V
CC
= 1.71 V to 3.6 V; GND = 0 V;
T
A
= 40°C to 85°C (Note 5)
Symbol Characteristic Min Typ Max Unit
POWER SUPPLY CURRENT
V
CC
Power Supply Voltage V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
3.135
2.375
1.71
3.3
2.5
1.8
3.6
2.625
1.89
V
I
CC
Power Supply Current (Inputs and Outputs Open) 170 210 mA
CML OUTPUTS (Note 6)
V
OH
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
– 30
3270
2470
1770
V
CC
– 5
3295
2495
1795
V
CC
3300
2500
1800
mV
V
OL
Output LOW Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
– 525
2775
1975
1275
V
CC
– 425
2875
2075
1375
V
CC
– 325
2975
2175
1475
mV
DIFFERENTIAL INPUT DRIVEN SINGLEENDED (see Figures 5 and 7) (Note 7)
V
IH
Singleended Input HIGH Voltage V
th
+ 100 V
CC
mV
V
IL
Singleended Input LOW Voltage GND V
th
100 mV
V
th
Input Threshold Reference Voltage Range (Note 8) 1050 V
CC
100 mV
V
ISE
Singleended Input Voltage Amplitude (V
IH
V
IL
) 200 2800 mV
VREFAC
V
REFAC
Output Reference Voltage @ 100 mA for capacitor* coupled inputs,
only (Note 9) V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
– 650
2650
1850
1150
V
CC
– 500
2800
2000
1300
V
CC
– 350
2950
2150
1450
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6 and 8) (Note 9)
V
IHD
Differential Input HIGH Voltage 1200 V
CC
mV
V
ILD
Differential Input LOW Voltage 0 V
IHD
100 mV
V
ID
Differential Input Voltage (V
IHD
V
ILD
) 100 1200 mV
V
CMR
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
1050 V
CC
50 mV
I
IH
Input HIGH Current IN / IN, (VT Open) 150 150
mA
I
IL
Input LOW Current IN / IN, (VT Open) 150 150
mA
CONTROL INPUTS (EQEN)
V
IH
Input HIGH Voltage for Control Pins V
CC
x 0.65 V
CC
V
V
IL
Input LOW Voltage for Control Pins GND V
CC
x 0.35 V
I
IH
Input HIGH Current 150 150
mA
I
IL
Input LOW Current 150 150
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 45 50 55
W
R
TOUT
Internal Output Termination Resistor 45 50 55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. CML outputs loaded with 50 W to V
CC
for proper operation.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in singleended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10.V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the crosspoint side of the differential input
signal.
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Table 6. AC CHARACTERISTICS V
CC
= 1.71 V to 3.6 V; GND = 0 V; T
A
= 40°C to 85°C (Note 11)
Symbol
Characteristic Min Typ Max Unit
f
MAX
Maximum Input Clock Frequency; V
OUT
w 200 mV 7 8.5 GHz
f
DATAMAX
Maximum Operating Data Rate NRZ, (PRBS23) 10 14 Gbps
V
OUTPP
Output Voltage Amplitude, EQEN = 0 or 1 (Note 15) f
in
7GHz
(See Figure 10)
200 400 mV
t
PLH
,
t
PHL
Propagation Delay IN to Q
x
125 175 225 ps
t
SKEW
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
3
15
15
50
ps
t
DC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
v 7GHz 40 50 60 %
F
N
Phase Noise, fin = 1 GHz 10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
134
136
150
151
151
151
dBc
t
ŐF
N
Integrated Phase Jitter f
in
= 1 GHz, 12 kHz 20 MHz
Offset (RMS)
35 fs
t
JITTER
RMS Random Clock Jitter (Note 13) f
in
v 7 GHz
PeaktoPeak Data Dependent Jitter (Note 14)
f
IN
14 Gbps EQEN = 0 (v 3” FR4)
f
IN
10 Gbps EQEN = 1 (12” FR4)
0.2 0.8
10
10
ps rms
ps pkpk
ps pkpk
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
100 1200 mV
t
r
t
f
Output Rise/Fall Times @ 1.0 GHz Qx, Qx
(20% 80%)
15 30 45 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing V
INPP
400mV from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% 80%).
12.Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peaktopeak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swings are singleended measurements operating in a differential mode.
600
500
400
300
200
100
0
0812 76534
Figure 3. CLOCK Output Voltage Amplitude (V
OUTPP
) vs. Input Frequency (f
in
) at Ambient Temperature (Typical)
f
in
, CLOCK INPUT FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE
(mV)
Q AMP (mV)
910

NB7VQ14MMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1.8/2.5/3.3V FANOUT
Lifecycle:
New from this manufacturer.
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