ADUM3160BRWZ Datasheet ADUM3160BRWZ-RL, ADUM3160BRWZ, ADUM3160WBRWZ-RL | P10-P12

Data Sheet ADuM3160

Rev. C | Page 9 of 16

APPLICATIONS INFORMATION

FUNCTIONAL DESCRIPTION

USB isolation in the D+/D− lines is challenging for several

reasons. First, access to the output enable signals is normally

required to control the transceiver. Some level of intelligence

must be built into the isolator to interpret the data stream and

determine when to enable and disable its upstream and down-

stream output buffers. Second, the signal must be faithfully

reconstructed on the output side of the coupler while retaining

precise timing and not passing transient states such as invalid

SE0 and SE1 states. In addition, the part must meet the low

power requirements of the suspend mode.

The iCoupler technology is based on edge detection and, therefore,

lends itself well to the USB application. The flow of data through

the device is accomplished by monitoring the inputs for activity

and setting the direction for data transfer based on a transition

from the idle state. After data directionality is established, data

is transferred until either an end of packet (EOP) or a sufficiently

long idle state is encountered. At this point, the coupler disables

its output buffers and monitors its inputs for the next activity.

During the data transfers, the input side of the coupler holds its

output buffers disabled. The output side enables its output buffers

and disables edge detection from the input buffers. This allows

the data to flow in one direction without wrapping back through

the coupler, causing the iCoupler to latch. Timing is based on the

differential input signal transition. Logic is included to eliminate

any artifacts due to different input thresholds of the differential

and single-ended buffers. The input state is transferred across

the isolation barrier as one of three valid states, J, K, or SE0. The

signal is reconstructed at the output side with a fixed time delay

from the input side differential input.

The iCoupler does not have a special suspend mode, nor does it

need one because its power supply current is below the suspend

current limit of 2.5 mA when the USB bus is idle.

The ADuM3160 is designed to interface with an upstream-facing

low/full speed USB port by isolating the D+/D− lines. An upstream-

facing port supports only one speed of operation; therefore, the

speed-related parameters, J/K logic levels, and D+/D− slew rate are

set to match the speed of the upstream-facing peripheral port

(see Table 10).

A control line on the downstream side of the ADuM3160

activates the idle state pull-up resistor. This allows the downstream

port to control when the upstream port attaches to the USB bus.

The PIN input can be tied to a 3.3 V control logic signal or to the

DD2

rail depending on whether enumeration must be controlled

or will occur when power is first applied.

PRODUCT USAGE

The ADuM3160 is designed to be integrated into a USB

peripheral with an upstream-facing USB port, as shown in

Figure 4. The key design points are as follows:

• The USB host provides power for the upstream side of the

ADuM3160 through the cable.

• The peripheral supply provides power to the downstream

side of the ADuM3160.

• The DD+/DD− lines of the isolator interface with the

peripheral controller, and the UD+/UD− lines of the

isolator connect to the cable or host.

• Peripheral devices have a fixed data rate that is set at design

time. The ADuM3160 has configuration pins, SPU and

SPD, that are set by the user to match this speed on the

upstream and downstream sides of the coupler.

• USB enumeration begins when either the D+ or D− line is

pulled high at the peripheral end of the USB cable. Control

of the timing of this event is provided by the PIN input on

the downstream side of the coupler.

• Pull-up and pull-down resistors are implemented inside

the coupler. Only external series resistors and bypass

capacitors are required for operation.

USB

HOST

ADuM3160

MICRO-

CONTROLLER

PERIPHERAL

POWER

SUPPLY

BUS

GND

BUS

D+

D–

D+

3.3V

D–

09125-004

Figure 4. Typical ADuM3160 Application

Other than the delayed application of pull-up resistors, the

ADuM3160 is transparent to USB traffic, and no modifications

to the peripheral design are required to provide isolation. The

isolator adds propagation delay to the signals comparable to a

hub and cable. Isolated peripherals must be treated as if there

were a built-in hub when determining the maximum number

of hubs in a data chain.

Hubs can be isolated like any other peripheral. Isolated hubs can be

created by placing an ADuM3160 on the upstream port of a hub

chip. This configuration can be made compliant if counted as two

hub delays. The hub chip allows the ADuM3160 to operate at full

speed yet maintain compatibility with low speed devices.

ADuM3160 Data Sheet

Rev. C | Page 10 of 16

COMPATIBILITY OF UPSTREAM APPLICATIONS

The ADuM3160 is designed specifically for isolating a USB

peripheral. However, the chip has two USB interfaces that meet

the electrical requirements for driving USB cables. This opens the

possibility of implementing isolation in downstream USB ports

such as isolated cables, which have generic connections to both

upstream and downstream devices, as well as isolating host ports.

In a fully compliant application, a downstream-facing port must

be able to detect whether a peripheral is low speed or full speed

based on the application of the upstream pull-up. The buffers

and logic conventions must adjust to match the requested speed.

Because the ADuM3160 sets its speed by hardwiring pins, the

part cannot adjust to different peripherals on the fly.

The practical result of using the ADuM3160 in a host port is

that the port works at a single speed. This behavior is acceptable

in embedded host applications; however, this type of interface is

not fully compliant as a general-purpose USB port.

Isolated cable applications have a similar issue. The cable operates

at the preset speed only; therefore, treat cable assemblies as custom

applications, not general-purpose isolated cables.

POWER SUPPLY OPTIONS

In most USB transceivers, 3.3 V is derived from the 5 V USB bus

through an LDO regulator. The ADuM3160 includes internal

LDO regulators on both the upstream and downstream sides. The

output of the LDO regulators is available on the V

DD1

and V

DD2

pins.

In some cases, especially on the peripheral side of the isolation,

there may not be a 5 V power supply available. The ADuM3160

has the ability to bypass the regulator and run on a 3.3 V supply

directly.

Two power pins are present on each side, V

BUSx

and V

DDx

. If 5 V

is supplied to V

BUSx

, an internal regulator creates 3.3 V to power

the xD+ and xD− drivers. V

DDx

provides external access to the

3.3 V supply to allow external bypass as well as bias for external

pull-ups. If only 3.3 V is available, it can be supplied to both V

BUSx

and V

DDx

. This disables the regulator and powers the coupler

directly from the 3.3 V supply.

Figure 5 shows how to configure a typical application when the

upstream side of the coupler receives power directly from the USB

bus and the downstream side receives 3.3 V from the peripheral

power supply. The downstream side can run from a 5 V V

BUS2

power supply as well. It can be connected in the same manner

as V

BUS1

, as shown in Figure 5, if needed.

PRINTED CIRCUIT BOARD LAYOUT

The ADuM3160 digital isolator requires no external interface

circuitry for the logic interfaces. For full speed operation, the D+

and D− lines on each side of the device require a 24 Ω ± 1% series

termination resistor. These resistors are not required for low speed

applications. Power supply bypassing is required at the input and

output supply pins (see Figure 5). Install bypass capacitors between

BUSx

and V

DDx

on each side of the chip. The capacitors should have

a minimum value of 0.1 µF and low ESR. The total lead length

between both ends of the capacitor and the power supply pin

should not exceed 10 mm.

Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15

should also be considered unless the ground pair on each package

side is connected close to the package. All logic level signals are

3.3 V and should be referenced to the local V

DDx

pin or 3.3 V logic

signals from an external source.

BUS1

GND

DD1

PDEN

SPU

UD–

UD+

GND

BUS2

GND

DD2

SPD

DD–

DD+

GND

ADuM3160

BUS1

= 5.0V INPUT

DD1

= 3.3V OUTPUT

BUS2

= 3.3V INPUT

DD2

= 3.3V INPUT

09125-005

Figure 5. Suggested PCB Layout Example

In applications that involve high common-mode transients, care

should be taken to minimize board coupling across the isolation

barrier. Furthermore, design the board layout such that any coupling

that does occur affects all pins equally on a given component side.

Failure to ensure this can cause voltage differentials between pins

that exceed the absolute maximum ratings of the device, thereby

leading to latch-up or permanent damage.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent to the decoder via the transformer.

The decoder is bistable and is, therefore, either set or reset by the

pulses, indicating input logic transitions.

The limitation on the magnetic field immunity of the ADuM3160

is set by the condition in which induced voltage in the receiving

coil of the transformer is sufficiently large to either falsely set or

reset the decoder. The following analysis defines the conditions

under which this may occur. The 3 V operating condition of the

ADuM3160 is examined because it represents the most suscep-

tible mode of operation.

Data Sheet ADuM3160

Rev. C | Page 11 of 16

The pulses at the transformer output have an amplitude greater

than 1.0 V. The decoder has a sensing threshold at approximately

0.5 V, thus establishing a 0.5 V margin in which induced voltages

can be tolerated. The voltage induced across the receiving coil is

given by

V = (−dβ/dt) ∑ πr

; n = 1, 2, … , N

where:

β is the magnetic flux density (gauss).

is the radius of the n

turn in the receiving coil (cm).

N is the number of turns in the receiving coil.

Given the geometry of the receiving coil in the ADuM3160 and

an imposed requirement that the induced voltage be, at most,

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated as shown in Figure 6.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001

100

100M

0.1

0.01

10k 100k 1M

10M

09125-006

Figure 6. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maxi-

mum allowable magnetic field of 0.2 kgauss induces a voltage of

0.25 V at the receiving coil. This voltage is approximately 50% of

the sensing threshold and does not cause a faulty output transition.

Similarly, if such an event occurs during a transmitted pulse (and

is of the worst-case polarity), it reduces the received pulse from

>1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of

the decoder.

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances from the ADuM3160 trans-

formers. Figure 7 expresses these allowable current magnitudes

as a function of frequency for selected distances. As shown in

Figure 7, the ADuM3160 is extremely immune and can be affected

only by extremely large currents operated at high frequency very

close to the component. For the 1 MHz example noted, a 0.5 kA

current must be placed 5 mm away from the ADuM3160 to affect

the operation of the device.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

0.1

0.01

1k 10k

100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

09125-007

Figure 7. Maximum Allowable Current

for Various Current-to-ADuM3160 Spacings

Note that at combinations of strong magnetic field and high

frequency, any loops formed by PCB traces may induce error

voltages sufficiently large to trigger the thresholds of succeeding

circuitry. Care should be taken in the layout of such traces to

avoid this possibility.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of insu-

lation degradation is dependent on the characteristics of the voltage

waveform applied across the insulation. In addition to the testing

performed by the regulatory agencies, Analog Devices carries out

an extensive set of evaluations to determine the lifetime of the

insulation structure within the ADuM3160.

Analog Devices performs accelerated life testing using voltage

levels higher than the rated continuous working voltage. Accel-

eration factors for several operating conditions are determined.

These factors allow calculation of the time to failure at the actual

working voltage. The values shown in Table 8 summarize the

peak voltage for 50 years of service life for a bipolar ac operating

condition and the maximum CSA/VDE approved working volt-

ages. In many cases, the approved working voltage is higher than

the 50-year service life voltage. Operation at these high working

voltages can lead to shortened insulation life in some cases.

The insulation lifetime of the ADuM3160 depends on the

voltage waveform type imposed across the isolation barrier.

The iCoupler insulation structure degrades at different rates

depending on whether the waveform is bipolar ac, unipolar ac,

or dc. Figure 8, Figure 9, and Figure 10 illustrate these different

isolation voltage waveforms.

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ADUM3160BRWZ

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