ADuM3160 Data Sheet
Rev. C | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
Storage Temperature (T
ST
) −40°C to +150°C
Ambient Operating Temperature (T
A
) −40°C to +105°C
Supply Voltages (V
BUS1
, V
BUS2
, V
DD1
,
V
DD2
)
1, 2
−0.5 V to +6.5 V
Input Voltage (V
UD+
, V
UD
, V
SPU
)
1
−0.5 V to V
DD1
+ 0.5 V
Output Voltage (V
DD
, V
DD+
, V
SPD
, V
PIN
)
1
−0.5 V to V
DD2
+ 0.5 V
Average Output Current per Pin
3
Side 1 (I
O1
) −10 mA to +10 mA
Side 2 (I
O2
) −10 mA to +10 mA
Common-Mode Transients
4
−100 kV/µs to +100 kV/µs
1
All voltages are relative to their respective grounds.
2
V
DD1
, V
DD2
, V
BUS1
, and V
BUS2
refer to the supply voltages on the input and
output sides of a given channel, respectively.
3
See Figure 2 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings may cause
latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 8. Maximum Continuous Working Voltage
1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform
Basic Insulation 560 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 849 V peak Maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 849 V peak Maximum approved working voltage per IEC 60950-1
1
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Data Sheet ADuM3160
Rev. C | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
BUS1
1
GND
1
*
2
V
DD1
3
PDEN
4
V
BUS2
16
GND
2
*
15
V
DD2
14
SPD
13
SPU
5
PIN
12
UD–
6
DD–
11
UD+
7
DD+
10
GND
1
*
8
GND
2
*
9
ADuM3160
T
O
P VIEW
(Not to Scale)
*PIN 2 AND PIN 8
ARE INTERNAL
LY
CONNECTED TO EACH OTHER, AND IT
IS RECOMMENDED THAT BOTH PINS BE CONNECTED T
O A
COMMON GROUND.
PIN 9
AND PIN 15
ARE INTERNALL
Y CONNECTED TO EACH OTHER, AND IT
IS RECOMMENDED THAT BOTH PINS BE CONNECTED
TO
A
COMMON GROUND.
09125-003
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Direction Description
1 V
BUS1
Power
Input Power Supply for Side 1. When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V),
connect the V
BUS1
pin to the USB power bus. When the isolator is powered from a 3.3 V power supply,
connect V
BUS1
to V
DD1
and to the external 3.3 V power supply. A bypass capacitor to GND
1
is required.
2 GND
1
Return
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
3 V
DD1
Power
Input Power Supply for Side 1. When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V),
the V
DD1
pin should be used for a bypass capacitor to GND
1
. Signal lines that may require pull-up, such
as PDEN and SPU, should be tied to this pin. When the isolator is powered from a 3.3 V power supply,
connect V
BUS1
to V
DD1
and to the external 3.3 V power supply. A bypass capacitor to GND
1
is required.
4 PDEN Input
Pull-Down Enable. This pin is read when exiting reset. This pin must be connected to V
DD1
for standard
operation. If this pin is connected to GND
1
when exiting reset, the downstream pull-down resistors
are disconnected, allowing buffer impedance measurements.
5 SPU Input
Speed Select, Upstream Buffer. Active high logic input. When SPU is tied high, the full speed slew
rate, timing, and logic conventions are selected; when SPU is tied low, the low speed slew rate,
timing, and logic conventions are selected. This input must be set high via connection to V
DD1
or set
low via connection to GND
1
and must match Pin 13 (both pins tied high or both pins tied low).
6 UD− Input/Output Upstream D−.
7 UD+ Input/Output Upstream D+.
8 GND
1
Return
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
9 GND
2
Return
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
10 DD+ Input/Output Downstream D+.
11 DD− Input/Output Downstream D−.
12 PIN Input
Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port.
It can be tied to V
DD2
for operation on power-up, or it can be tied to an external control signal for an
application that requires delayed enumeration.
13
SPD
Input
Speed Select, Downstream Buffer. Active high logic input. When SPD is tied high, the full speed
slew rate, timing, and logic conventions are selected; when SPD is tied low, the low speed slew rate,
timing, and logic conventions are selected. This input must be set high via connection to V
DD2
or set
low via connection to GND
2
and must match Pin 5 (both pins tied high or both pins tied low).
14 V
DD2
Power
Input Power Supply for Side 2. When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V),
the V
DD2
pin should be used for a bypass capacitor to GND
2
. Signal lines that may require pull-up,
such as SPD, can be tied to this pin. When the isolator is powered from a 3.3 V power supply, connect
V
BUS2
to V
DD2
and to the external 3.3 V power supply. A bypass capacitor to GND
2
is required.
15 GND
2
Return
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each
other, and it is recommended that both pins be connected to a common ground.
16 V
BUS2
Power
Input Power Supply for Side 2. When the isolator is powered by the USB bus voltage (4.5 V to 5.5 V),
connect the V
BUS2
pin to the USB power bus. When the isolator is powered from a 3.3 V power supply,
connect V
BUS2
to V
DD2
and to the external 3.3 V power supply. A bypass capacitor to GND
2
is required.
ADuM3160 Data Sheet
Rev. C | Page 8 of 16
Table 10. Truth Table, Control Signals, and Power (Positive Logic)
V
SPU
Input
1
V
UD+
, V
UD
State
1
V
BUS1
, V
DD1
State
V
BUS2
, V
DD2
State
V
DD+
, V
DD−
State
1
V
PIN
Input
1
V
SPD
Input
1
Description
High Active Powered Powered Active High High
Input and output logic set for full speed logic
convention and timing.
Low
Active
Powered
Powered
Active
High
Low
Input and output logic set for low speed logic
convention and timing.
Low Active Powered Powered Active High High
Not allowed. V
SPU
and V
SPD
must be set to the same
value. The USB host detects a communication error.
High Active Powered Powered Active High Low
Not allowed. V
SPU
and V
SPD
must be set to the same
value. The USB host detects a communication error.
X Z Powered Powered Z Low X
Upstream Side 1 presents a disconnected state to
the USB cable.
X X Unpowered Powered Z X X
When power is not present on V
DD1
, the down-
stream data output drivers revert to the high-Z
state within 32 bit times. The downstream side
initializes in the high-Z state.
X Z Powered Unpowered X X X
When power is not present on V
DD2
, the upstream
side disconnects the pull-up and disables the
upstream drivers within 32 bit times.
1
X is don’t care; Z is the high impedance output state.

ADUM3160BRWZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Full/Low Spd USB 2.0 Digital
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union