SI51214-A01AFM Datasheet SI51214-A01AFM, SI51214-A01AFMR, SI51214-A1FAGM | P1-P3

Si51214 Data Sheet

Two Output Factory Programmable Clock Generator

The factory programmable Si51214 is the industry’s lowest power, smallest footprint and

frequency flexible programmable clock generator targeting low power, low cost and high

volume consumer and embedded applications. The device operates from a single crys-

tal or an external clock source and generates 1 to 2 outputs up to 133 MHz. The device

is factory programmed to provide customized output frequencies and control input such

as frequency select, spread spectrum on, power down and output enable. Center spread

spectrum can also be programmed to reduce EMI to meet board level system require-

ments.

KEY FEATURES

• Generates up to 2 CMOS clock outputs

from 3 to 133 MHz

• Accepts crystal or reference clock input

• 3 to 165 MHz reference clock input

• 8 to 48 MHz crystal input

• Programmable FSEL, SSONb, PD, and OE

input functions

Applications

• Crystal/XO replacement

• EMI reduction

• Portable devices

• Digital still camera

• IP phone

• Smart meter

To Pin 4 and Pin

To Core

Programmable

Configuration

PLL with

Modulation

Control

Buffers,

Dividers,

and

Switch

Matrix

SSCLK1/

REFCLK/

OE/FSEL/SSONb

SSCLK2/OE/

SSONb/PD

XIN/

CLKIN

XOUT

VDD

VSS

V-REG

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1. Feature List

The Si51214 highlighted features are listed below.

• Generates up to 2 CMOS clock outputs from 3 to 133 MHz

• Accepts crystal or reference clock input

• 3 to 165 MHz reference clock input

• 8 to 48 MHz crystal input

• Programmable FSEL, SSONb, PD, and OE input functions

• Low power dissipation

• 1.8 V voltage supply range

• ±0.25%, ±0.5% or ±1% spread spectrum (center spread)

• Low cycle-cycle jitter

• Ultra small 6-pin TDFN package (1.2 mm x 1.4 mm)

Si51214 Data Sheet

Feature List

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2. Design Considerations

2.1 Typical Application Schematic

2.2 Comments and Recommendations

Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pin 1. Place the capacitor on the

component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as

short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be placed

between VDD and VSS.

Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK

pins) and the load is over 1 ½ inches. The nominal impedance of the SSCLK output is about 30 Ω. Use a 20 Ω resistor in series with the

output to terminate a 50 Ω trace impedance and place a 20 Ω resistor as close to the SSCLK output as possible.

Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the

crystal initial accuracy specification (in ppm) make sure that the external crystal load capacitor is matched to the crystal load specifica-

tion. To determine the value of CL1 and CL2, use the following formula:

CL1 = CL2 = 2CL − (Cpin + Cp);

where CL is the load capacitance stated by the crystal manufacturer,

Cpin is the Si51214 pin capacitance (3 pF), and

Cp is the parasitic capacitance of the PCB traces.

Example: If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 or 20 pF external

capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp value.

Table 2.1. Crystal Specifications

Equivalent Series Resistance (ESR) Crystal Output Capacitance (CO) Load Capacitance (CL)

< 50 Ω < 3 pF < 13 pF

Si51214 Data Sheet

Design Considerations

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

SI51214-A01AFM

Mfr. #:

Buy SI51214-A01AFM

Manufacturer:

Silicon Labs

Description:

Clock Generators & Support Products 2-output Programmable Clock Generator

Lifecycle:

New from this manufacturer.

Delivery:

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SI51214-A01AFM

SI51214-A01AFM

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